International Business Machines Corporation

Infineon Technologies Ag

Henry Atkinson Nye, Iii

Stephen James Kilpatrick

Vincent James McGahay

Da-Yuan Shih

Donna S Zupanski-Nielsen

Daniel C Edelstein

Keith E Fogel

Paul Alfred Lauro

Jeffrey F Roeder

Sung Kwon Kang

Balaram Ghosal

Timothy Harrison Daubenspeck

Christopher Vincent Jahnes

Emanuel Israel Cooper

William Thomas Motsiff

Thomas L McDevitt

Ho-Ming Tong

Charles Robert Davis

Joyce C Liu

Paul A Totta

Charles C Goldsmith

Lisa A Fanti

Thomas H Ivers

Carmen M Mojica

Sanjay C Mehta

John Michael Cotte

John Anthony Fitzsimmons

Hans-Joachim Barth

David Lee Rath

Jeffrey Curtis Hedrick

Carlos Juan Sambucetti

Phillip John Restle

Stephan Grunow

Madhav Datta

Donald W Henderson

Yu-Ting Cheng

Douglas Wayne Kemerer

Birendra N Agarwala

Brett H Engel

Richard Andre Wachnik

Stefanie Ruth Chiras

David E Eichstadt

Lloyd G Burrell

Joseph L Chan

William H Price

Michael A Russak

John C Hay, Jr

Theodore Harold Zabel

Emmanuel F Crabbe

Kurt Alan Tallman

Gerald G Advocate, Jr

David K Anderson

Sung-Kwon Kang

Richard E Gegenwarth

Brian George Ottey

Patrick M Miller

Emanual I Cooper

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via 'anchors' (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration ('drilling, gouging') into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

Structure and method of chemically formed anchored metallic vias

A first metal is plated onto a substrate comprising a second metal by immersing the substrate into a bath comprising a compound of the first metal and an organic diluent. The second metal is more electropositive than the first metal. The organic diluent has a boiling point higher than a eutectic point in a phase diagram of the first and second metals. The bath is operated above the eutectic point but below the melting point of the second metal. For example, bismuth is immersion plated onto lead-free tin-based solder balls, and subsequently redistributed by fluxless reflow. Plated structures are also provided.

Immersion plating and plated structures

A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure

A semiconductor device having at least one fuse and an alignment mark formed therein. An etch resistant layer over the surface of the fuse and alignment mark, which provides a uniform passivation thickness for use in conjunction with laser fuse deletion processes.

Insulative cap for laser fusing

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

Support structures for wirebond regions of contact pads over low modulus materials

A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

Inhibition of tin oxide formation in lead free interconnect formation

Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Method for improving adhesion to copper

An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Alpha particle shield for integrated circuit

A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

Hybrid dielectric structure for improving the stiffness of back end of the line structures

A bond pad structure for an integrated circuit has bondable base member for receiving a wire bonded thereon. A cavity is formed within the base member, with the cavity being configured to capture the wire therein. The cavity has one end having a first width and an opposite end having a second width, with the first width being greater than second width.

Bond pad structure and method for reduced downward force wirebonding

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Brookfield, CT, United States of America

Henry Atkinson Nye, Iii