Industrial Technology Research Institute

Heng-Yuan Lee

Yu-Sheng Chen

Po-Chun Yeh

Frederick Chen

Lurng-Shehng Lee

Pang-Shiu Chen

Chieh-Shuo Liang

Ching-Chiun Wang

Tai-Yuan Wu

Yu-De Lin

Hsin-Yun Yang

Tuo-Hung Hou

Chih-Yao Wang

Chuan-Wei Tsou

Yen-Ya Hsu

Kan-Hsueh Tsai

Ching-Chih Hsu

Shyh-Shyuan Sheu

Chih-Sheng Lin

Wei-Su Chen

Ming-Jinn Tsai

Jeng-Hua Wei

Yi-Keng Fu

Pei-Jer Tzeng

Jian-Wei Su

Fu-Cheng Tsai

Ming-Hung Wu

Hsueh-Hsing Liu

Ching-Yuan Ho

Pei-Yi Gu

Han-Chieh Ho

A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.

Neuron circuit and artificial neural network chip

A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

Ferroelectric memories

A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

Computation operator in memory and operation method thereof

A ferroelectric memory is provided. The ferroelectric memory includes a first electrode layer having a dominant crystallographic orientation of () or (), a second electrode layer opposite the first electrode layer, wherein the second electrode layer has a dominant crystallographic orientation of () or (), and a ferroelectric layer disposed between the first electrode layer and the second electrode layer, wherein the ferroelectric layer has a dominant crystallographic orientation of ().

A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.

A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.

Structure of GaN-based transistor and method of fabricating the same

This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 &#x3bc;m and a height between 1 and 500 &#x3bc;m.

Structure of epitaxial wafer and method of fabricating the same

A III-nitride based semiconductor structure includes a substrate; a buffer layer disposed above the substrate; a first gallium nitrite (GaN) layer disposed above the buffer layer and including p-type GaN; a second GaN layer disposed on the first GaN layer and including at least a first region and a second region; a channel layer disposed above the second GaN layer; a barrier layer disposed above the channel layer; and a gate electrode disposed above the barrier layer. The first region of the second GaN layer is positioned correspondingly to the gate electrode and includes n-type GaN having a first doping concentration. The second region of the second GaN layer (such as the lateral portion of the second GaN layer) is positioned correspondingly to the areas outsides the gate electrode and includes n-type GaN having a second doping concentration larger than the first doping concentration.

III-nitride based semiconductor structure

A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Memory cell of resistive random access memory and manufacturing method thereof

A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Resistive random access memory and method for fabricating the same

A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

Control method for memory cell

A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.

Resistive memory and program verification method thereof

A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.

Resistive random access memory cell and resistive random access memory module

A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.

Growing community of inventors

Tainan County, Taiwan

Heng-Yuan Lee