Tokyo Electron Limited

Henan Zhang

Shan Hu

Sangita Kumari

Peter Delia

Eric Chih-Fang Liu

Yun Han

Robert Daniel Clark

Angelique Denise Raley

David L O'Meara

Andrew W Metz

Xinghua Sun

Hiroaki Niimi

Kandabara N Tapily

Akiteru Ko

Gerrit J Leusink

Cory Wajda

Kai-Hung Yu

Subhadeep Kal

Shihsheng Chang

Yen-Tien Lu

Hiroyuki Suzuki

Gyanaranjan Pattanaik

Ying Trickett

Michael Edley

Cheryl Alix

Embodiments of improved process flows and methods are provided in the present disclosure to form air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etch process to form recesses between metal interconnects formed on a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD) dependent etching provided by wet etch processes to etch an intermetal dielectric material formed between the metal interconnects at a faster rate than the intermetal dielectric material is etched in surrounding areas of the patterned substrate. This enables the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between the metal interconnects without using a dry etch process.

Wet etch process and methods to form air gaps between metal interconnects

A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.

Sacrificial capping layer for gate protection

Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material within high aspect ratio features. In the present disclosure, a wet etch process is used to etch material within high aspect ratio features, such as deep trenches and holes, provided on a patterned substrate. Uniform wet etching is provided in the present disclosure by ensuring that wall surfaces of the material being etched (or wall surfaces adjacent to the material being etched) exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

Methods to provide uniform wet etching of material within high aspect ratio features provided on a patterned substrate

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

Methods to prevent surface charge induced cd-dependent etching of material formed within features on a patterned substrate

Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

Wet etch process and method to control fin height and channel area in a fin field effect transistor (FinFET)

The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Methods for planarizing a substrate using a combined wet etch and chemical mechanical polishing (CMP) process

Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.

Wet etch process and method to provide uniform etching of material formed within features having different critical dimension (CD)

In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

Localized etch stop layer

In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.

Forming a semiconductor feature using atomic layer etch

A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

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Clifton Park, NY, United States of America

Henan Zhang