Silicon Access Networks, Inc.

Nsoft Systems, Inc.

Hemraj K Hingarh

Subramani Kengeri

Ven L Lee

A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

DRAM based refresh-free ternary CAM

A dynamic random access memory (DRAM) having a conventional cell layout and having its data access path adapted to access a 'zero' faster than a 'one.' The DRAM comprising two capacitors coupled respectively to two neighboring word lines. The two capacitors are also coupled respectively to two neighboring bit lines via two pass gates. Data is represented as complementary data bits on the two capacitors. In so doing, a &lsquo;zero&rsquo; is ensured to be stored in either one of the two capacitors. A voltage level &lsquo;zero&rsquo; is in turn ensured to be maintained on the bit line coupled to the capacitor that stores the &lsquo;zero&rsquo; data bit. The sense amplifier and the write driver take advantage of the fact that a voltage level &lsquo;zero&rsquo; is ensured to be maintained in either one of the two bit lines. Each of a sense amplifier and a write driver, as parts of the DRAM's data access path, amplifies a &lsquo;zero&rsquo; and a &lsquo;one&rsquo; unequally by amplifying the &lsquo;zero&rsquo; faster than the &lsquo;one.&rsquo; Access time is thus improved. The DRAM does not need to operate in the differential sensing mode. The DRAM can operate in either the differential sensing mode or the conventional mode. The switch between the differential and the conventional sensing modes can be implemented without having to alter the cell layout of a conventional DRAM.

Read zero DRAM

A unique gate array cell and ASIC library development methodology is taught which require no new simulations or new place and route to port a given device design to a same generation process technologies which are available from different vendors. This methodology make use of the minimum design rules from different vendors without reroute of the physical database. This methodology equalizes the functionality and timing characteristics of the macrocell library on a plurality of alternate sources.

Growing community of inventors

Saratoga, CA, United States of America

Hemraj K Hingarh