International Business Machines Corporation

Other

Hemen R Shah

Sebastian Theodore Ventrone

Igor Arsovski

Joseph Andrew Iadanza

Serafino Bueti

Hayden C Cranford, Jr

Todd Edwin Leonard

Anthony Richard Bonaccio

Pradeep Thiagarajan

Jason Michael Norman

Edward Butler

Robert Tamlyn

Alfred L Sartwell

Martin B Lundberg

Joseph A Iandanza

Pushkar U Mokashi

Robert B Goodwin

Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

Method and systems of powering on integrated circuit

Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.

Critical path redundant logic for mitigation of hardware across chip variation

An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

Design structures of powering on integrated circuit

A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

Design structures, method and systems of powering on integrated circuit

An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.

No latency pipeline

A high performance latch for read and write operations in RAM having a Complimentary Interlock circuit that eliminates the need for external timing to the RAM which might limit its high performance operation. For both read and write operations, the complementary interlock circuit extends a latching signal until valid data appears on the read or write data lines, thus preventing a valid data miss.

Growing community of inventors

South Burlington, VT, United States of America

Hemen R Shah