Lam Research Corporation

Helene Del Puppo

Gowri Kamarthy

Alex Paterson

Harmeet Singh

Vahid Vahedi

Saurabh J Ullal

Alan Jeffrey Miller

Yoshie Kimura

Frank Lin

Monica Titus

Nicolas Gani

Radhika C Mani

Chris Lee

Noel Sun

Do Young Kim

Thomas A Kamp

Jen-Kan Yu

Ting-Ying Chung

Ganesh Upadhyaya

Qinghua Zhong

Ming-Shu Kuo

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Internal plasma grid applications for semiconductor fabrication

Systems and methods for etching a substrate include arranging a substrate including a first structure and a dummy structure in a processing chamber. The first structure is made of a material selected from a group consisting of silicon dioxide and silicon nitride. The dummy structure is made of silicon. Carrier gas is supplied to the processing chamber. Nitrogen trifluoride and molecular hydrogen gas are supplied to the processing chamber. Plasma is generated in the processing chamber. The dummy structure is etched.

Residue free systems and methods for isotropically etching silicon in tight spaces

Internal plasma grid applications for semiconductor fabrication in context of ion-ion plasma processing

A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Method to improve profile control and N/P loading in dual doped gate applications

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Fremont, CA, United States of America

Helene Del Puppo