Siemens Aktiengesellschaft

Infineon Technologies Ag

Heinz Honigschmid

Georg Braun

Carlos Mazure-Espejo

Andrej Majdic

The invention relates to a memory configuration comprising a multiplicity of memory cells. Each of the memory cells has at least one ferroelectric storage capacitor and a selection transistor. The memory cells are addressed via word lines and bit line pairs. It is possible for a reference signal obtained from a reference cell pair via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier. The sense amplifier is thereby assigned two bit line pairs connected in such a way that the reference signal is applied via the first bit line pair and, at the same time, the read signal is applied via the second bit line pair to the sense amplifier.

Ferroelectric memory configuration

An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.

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Starnberg, Germany

Heinz Honigschmid