Infineon Technologies Ag

Siemens Aktiengesellschaft

Heinz H&ouml;nigschmid

Georg Braun

Thomas R&ouml;hr

Thomas B&ouml;hm

Zoltan Manyoki

Helmut Kandolf

Stefan Lammers

Ernst Neuhold

Kurt Hoffmann

Dietmar Gogl

Oskar Kowarik

Tobias Schlager

Robert Esterl

Christine Dehm

Gerhard M&uuml;ller

Marc Ullmann

Andrej Majdic

A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.

Random access semiconductor memory with reduced signal overcoupling

A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

Magnetic memory configuration

The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an increased channel width.

MRAM configuration having selection transistors with a large channel width

The data memory has a plurality of banks, each with a multiplicity of memory cells that form a matrix of rows and columns with respectively assigned matrix row lines and column lines. The banks are arranged spatially one on top of the other as stacks, with the stack edges that are parallel to the matrix rows and at which the ends of the column lines that are connected to a respective column-driving device are located, lie in a common plane. The common plane extends in the direction of the matrix rows and is substantially orthogonal with respect to the direction of the columns. The column-driving devices of all the banks are arranged directly adjacent to one another as a block in the direction of the columns, on or near the same edge of the bank stack. The banks preferably contain memory cells which can be read out without damage, and in each case a plurality of column lines are each assigned to one common sense amplifier in the column-driving device of each bank.

Data memory with a plurality of memory banks

An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

Ferroelectric memory configuration and a method for producing the configuration

An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.

Integrated memory with memory cell array

In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

Process for producing a capacitor configuration

A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic &ldquo;1&rdquo; or &ldquo;0&rdquo; flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration

A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.

Fuse circuit configuration

An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

Integrated memory and corresponding operating method

The invention relates to a method for operating a ferroelectric memory configuration in the V /2 mode. The memory configuration has a large number of memory cells which each have at least one selection transistor, one storage capacitor with an upper and a lower electrode and one short-circuiting transistor whose source-drain junction is connected in parallel with the storage capacitor. After a read or write procedure in which the memory cells are driven via respectively associated word lines and via respectively associated bit lines which are precharged in a precharge phase, the short-circuiting transistor is driven during a standby phase and in the process short-circuits the electrodes in the storage capacitor. The method is characterized in that the time of the standby phase coincides with the time of the precharge phase and, in the process, the bit lines are at a different potential with respect to that of the two electrodes of the storage capacitor.

Method for operating a ferroelectric memory configuration and a ferroelectric memory configuration

An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Integrated memory with redundancy

An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

Integrated semiconductor memory having memory cells with a ferroelectric memory property

A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer. A second transistor is inserted in parallel with the driver transistors, which form a first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated in a test mode.

Circuit configuration and method for accelerating aging in an MRAM

The integrated memory has driver units DRVi, via which the column select lines CSLi are connected to the plate line segments PLi and which, as a function of the potential of the associated column select lines CSLi and the word addresses RADR on the plate line segments PLi connected to them, generate potentials which have defined values for each operating state of the memory.

Growing community of inventors

East Fishkill, NY, United States of America

Heinz Hönigschmid

Growing community of inventors

East Fishkill, NY, United States of America

Heinz H&ouml;nigschmid

Heinz Hönigschmid