Sandisk Technologies Inc.

Heguang Li

Deepanshu Dutta

Lito De La Rama

Xiaochen Zhu

Hiroyuki Mizukoshi

Qihan Li

Althaf Rahamathulla

Suanbin Loh

Yuanyuan Wu

A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

Dual-way sensing scheme for better neighboring word-line interference

Technology is disclosed herein for early erase termination as a counter-measure for erase disturb. Multiple erase blocks of NAND memory cells are erased in parallel during an erase procedure. Erasing multiple erase blocks in parallel can place considerable strain on the circuitry that generates the erase voltage. If there is significant leakage current in one of the erase blocks the magnitude of the erase voltage for all of the erase blocks may drop. The erase blocks are tested sequentially for leakage current during the first erase loop while the erase voltage is applied to only the erase block under test. If any erase block fails the leakage current test that erase block is removed from the erase procedure. One or more additional erase loops are then performed with only those erase blocks that passed the leakage current test simultaneously receiving an erase voltage, thereby preventing erase disturb with early termination.

NAND early erase termination based on leakage current test

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

Nonvolatile memory with data recovery

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Newark, CA, United States of America

Heguang Li