Samsung Electronics Co., Ltd.

Heesook Park

Nam-Gun Kim

Eun-Ok Lee

Hyun-jung Lee

Gyuhwan Oh

Kyungho Jang

Janghee Lee

Mansug Kang

Dongchan Lim

Seonghwee Cheong

Myung-ho Kong

Youngwook Park

Jaehwa Park

Geumjung Seong

Byunghak Lee

Taeho Cha

Taekjung Kim

Hyun-Suk Lee

Sanghoon Ahn

Kyu-Hee Han

Jin-Su Lee

Gihee Cho

Jongmyeong Lee

Jun Kwan Kim

Dongkyun Park

JaeWha Park

Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

Semiconductor device

A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MON, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.

Capacitor and a semiconductor device including the same

A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Semiconductor devices including metal-silicon-nitride patterns

A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Semiconductor devices including spacers

Methods of manufacturing semiconductor devices including air gap spacers

Semiconductor devices including air gap spacers

In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer.

Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method

Dual gate structure, fabrication method for the same, semiconductor device having the same

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Hwaseong-si, South Korea

Heesook Park