Skhynix Inc.

Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Hyundai Motor Company

Samsung Electronics Co., Ltd.

Kia Motors Corporation

Nautilus Hyosung Inc.

Hyundai Electronics Ind. Co., Ltd.

Keyang Electric Machinery Co., Ltd.

Motonic Corporation

Pyeong Hwa Valeo Co., Ltd.

Hee Youl Lee

Ji Hyun Seo

Hee Hyun Chang

Han Soo Joo

Ji Ho Park

Dong Hun Lee

Bong Yeol Park

Kwang Min Lim

Sang Hyun Oh

Min Kyu Jeong

Sung Jae Chung

Se Hoon Kim

Sung Yong Chung

Sung Ho Bae

Kyung Sik Mun

Kyoung Cheol Kwon

Sung In Hong

Ki Jun Kim

Yeonho Kim

Yeon Ho Kim

Baekyu Kim

Min Kyu Lee

Ki Seog Kim

Se Jun Kim

Jung Shik Jang

Yu Jin Jung

Byung Jin Ahn

Tae Gyun Kim

Tushar Balasaheb Sandhan

Dong Kee Lee

Jae Bum Park

Hyun Seung Yoo

Won Sic Woo

Kyoung Bum Kim

Dae Kyu Shin

Hyun Heo

Taewon Kim

Sang Hwa Do

Tae Soo Lee

Sang Heon Lee

Byung In Lee

Hea Jong Yang

Hye Eun Heo

Yong Dae Park

Jae C An

Jinho Jang

Young Hwan Choi

Nyeon Han Hong

Namhun Lee

Bum Taek Lim

Young Su Seo

Man-Dae Hur

Wookyo Jang

Dong Jin Choi

Junglyung Choi

Myung-Kweon Kang

Yoon-Sub So

Hongcheol Moon

Chang-Hwa Kim

Je Bock Chung

Dong Kyu Kim

Hye Min Song

Young Ki Shin

Byeong Kyu Cho

Chul Young Ham

Jun Tae Lee

Jae Yoon Noh

Jeong Su Lee

Jeong Hyong Yi

Byung Soo Park

A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks coupled to a common source line. The peripheral circuit performs a program operation on a memory block selected from among the memory blocks. The control logic controls the program operation of the peripheral circuit. The memory blocks are coupled to corresponding source select lines, respectively. The program operation includes a plurality of program loops, each including a channel precharge operation. During the channel precharge operation, the control logic controls the peripheral circuit so that the common source line floats and a voltage of a source select line coupled to an unselected memory block, among the memory blocks, is increased.

Semiconductor memory device performing program operation and method of operating the same

A memory includes a cell string including a first select transistor, cell transistors, and a second select transistor and a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors. The row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor.

Memory configured to perform a channel precharge operation and method of operating the memory

The present disclosure relates to a memory device, and a method of operating the memory device that includes a memory block including memory cells. The memory device also includes a voltage generator configured to apply a read voltage and pass voltages to word lines coupled to the memory block. The voltage generator is configured to apply the read voltage to a selected word line among the word lines and apply different pass voltages to unselected word lines symmetrical to each other with respect to the selected word line depending on distances to the selected word line, during a read operation on the memory block.

Memory device and method of operating the same

A memory device, and a method of operating the memory device, includes a memory block including strings formed between bit lines and a source line and includes a peripheral circuit configured to perform a read operation of a selected memory cell included in a selected string among the strings. The peripheral circuit includes page buffers configured to increase a voltage of channels of the strings by applying a first precharge voltage to the bit lines in a set-up phase of the read operation, apply a second precharge voltage lower than the first precharge voltage to the bit lines in a read phase of the read operation, and discharge the bit lines in a discharge phase of the read operation.

Memory device and operating method of the memory device for controlling a channel voltage

Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

Memory device for selecting memory block according to amount of data and operating method of the same

There are provided a memory device and an operating method of the memory device. The memory device includes: a first select transistor, a plurality of memory cells, and a second select transistor, connected between a source line and a bit line; and a peripheral circuit for performing a pre-program operation on the plurality of memory cells and then performing an erase operation on the plurality of memory cells. In the pre-program operation, the peripheral circuit is configured to apply a program voltage to word lines that are connected to the plurality of memory cells corresponding to a channel that has been floated.

Memory device and operating method of the memory device

A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes dummy memory cells connected to dummy word lines and normal memory cells connected to normal word lines. The peripheral circuit performs an erase operation on the memory block. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first dummy memory cells connected to first dummy word lines among the dummy word lines, in response to an erase command for the memory block, and perform a pre-program operation on second dummy memory cells connected to second dummy word lines among the dummy word lines, after the pre-program operation on the first dummy memory cells. The control logic controls the peripheral circuit to perform an erase operation on the normal memory cells.

Semiconductor memory device and operating method thereof

Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block including memory cell strings, a voltage supply circuit configured to apply operating voltages to global drain select lines, global source select lines, and global word lines, and apply an erase voltage to bit lines or to the bit lines and a source line during an erase operation, a pass circuit configured to couple the global drain select lines, global source select lines, and global word lines to local drain select lines, local source select lines, and local word lines in response to a block select signal, and control logic configured to control the voltage supply circuit to apply a first operating voltage to the global drain select lines and thereafter apply a second operating voltage to the global drain select lines.

Semiconductor memory device with voltages applied to global drain select lines and method of operating the semiconductor memory device

A method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. A first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.

Semiconductor memory device and method of operating the semiconductor memory device

Provided herein is a memory device, a memory system including the memory device, and a method of operating the memory system. The memory device including a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks, peripheral circuits configured to perform a program operation on a memory block selected from among the plurality of memory blocks and configured to, when a program failure occurs during the program operation, move and store first data stored in a failed sub-block in which the program failure has occurred, among the plurality of sub-blocks, to a replacement block, among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform the program operation and generate bad block information from information about the failed sub-block.

Method and system for reuse of partial bad block

Semiconductor memory device and method of operating the same whereby the voltage of a floated common source line is increased by increasing the voltage of a source select line coupled to an unselected memory block

A method of operating a semiconductor memory device programming selected memory cells to store bits of data in each of the selected memory cells includes foggy programming and fine programming.

Semiconductor memory device and operating method of the semiconductor memory device

A semiconductor memory device includes a first cell string, a second cell string, a peripheral circuit, and a control logic. The first cell string includes first and second drain select transistors. The second cell string includes third and fourth drain select transistors. The peripheral circuit performs a program operation on the fourth drain select transistor included in the second cell string. The threshold voltage of the first drain select transistor is set through an ion implantation process. The threshold voltage of the fourth drain select transistor is set through the program operation.

Method of programming a select transistor of a semiconductor memory device

A method of operating a semiconductor memory device includes performing a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program phase and a verify phase. The program phase includes setting a state of a select line connected to a selected memory block including the selected memory cells, wherein setting the state of the select line connected to the selected memory block comprises applying a voltage to the select line based on a program progress state of the selected memory cells, setting a state of a bit line connected to the selected memory block, applying a program voltage to a selected word line among word lines connected to the selected memory block and applying a pass voltage to an unselected word line.

Semiconductor memory device for applying voltage to select line based on number of times program loops are performed and method of operating the same

A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

Semiconductor memory device

Growing community of inventors

Icheon-si, South Korea

Hee Youl Lee