Altera Corporation

Intel Corporation

Hee Kong Phoon

Kar Keng Chua

Chee Hak Teh

Lai Guan Tang

Bee Yee Ng

Sammy S Cheung

Chee Seng Leong

Kim Pin Tan

Han Wooi Lim

Wei Lian Goay

Teik Hong Ooi

Guan Hoe Oh

Boon Jin Ang

Wei Yee Koay

Kian Chin Yap

Beng Lee Ooi

The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

Fabric die to fabric die interconnect for modularized integrated circuit devices

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.

Power gated lookup table circuitry

An integrated circuit includes a delay circuit, a buffer circuit, and a storage circuit. The delay circuit delays a first timing signal to generate a second timing signal. The buffer circuit generates a third timing signal for transmission to an external device. The third timing signal is generated based on the first timing signal. The external device provides data to the integrated circuit based on the third timing signal. The storage circuit captures the data transmitted from the external device in response to the second timing signal.

Timing signal adjustment for data storage

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ('HLEs'), each of which can provide a portion of the full functionality of an FPGA logic element ('LE'). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Application-specific integrated circuit equivalents of programmable logic and associated methods

Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.

Methods and apparatus for programmably powering down structured application-specific integrated circuits

A mask-programmable logic device includes a macrocell having an external input/output port for 'place-and-route' programming by addition of metallization layers. A programmable 'fixed' layer allows the external input/output port to be isolated from the remainder of the macrocell so that it &#x201c;floats,&#x201d; allowing signals to be routed through the external input/output port when the macrocell is not in use, to reduce routing blockages. The macrocell also may have at least one internal input/output port, potentially connected to different logic circuits, and a programmable &#x201c;fixed&#x201d; layer that can be used to control which internal input/output port is connected to the external input/output port. By thus allowing multiple logic circuits to share a single external input/output port, routing blockages are reduced.

Mask-programmable logic device with programmable input/output ports

A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.

Growing community of inventors

Perak, Malaysia

Hee Kong Phoon