Raytheon Company

Heather D Leifeste

Ron C Stevens

Christopher T Moshenrose

Andreas Hampp

Paul A Drake

Tamara H Wright

A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.

Eliminating interconnect strains in microcircuits

An apparatus includes a base configured to receive at least one component. The apparatus also includes a handle connected to the base and extending away from the base. The apparatus further includes a clip configured to slide along at least part of the handle towards and away from the base. The clip is configured to secure the at least one component to the apparatus and to release the at least one component from the apparatus. The clip is configured, after the at least one component is secured, to be locked in order to prevent release of the at least one component from the apparatus. The handle may include a lock configured to selectively prevent movement of the clip along the handle passed the lock.

Paddle tool for transporting semiconductor wafers or other components

Handheld semiconductor wafer handling tool

In certain embodiments, a method includes forming a composite semiconductor structure for altering a rate of thermal expansion of a first substrate. The composite semiconductor structure is formed by atomically bonding a first surface of a thermal matching substrate to a first surface of the first substrate, and atomically bonding a second surface of the thermal matching substrate to a first surface of a balancing substrate. The thermal matching substrate is adapted to alter the rate of thermal expansion of the first substrate and the balancing substrate is adapted to substantially prevent warping of the composite semiconductor structure.

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Santa Barbara, CA, United States of America

Heather D Leifeste