Applied Materials, Inc.

Micro Materials Inc.

Applied Material, Inc.

Mirocmaterials LLC

He Ren

Mehul B Naik

Hao Jiang

Srinivas D Nemani

Yong Cao

Yu Lei

Bencherki Mebarki

Mei-Yee Shek

Uday Mitra

Yana Cheng

Minrui Yu

Shi You

Hao Chen

Kai Wu

Regina Germanie Freed

Yi Xu

Ellie Y Yieh

Deenesh Padhi

Sean S Kang

Chentsau Chris Ying

Naomi Yoshida

Amrita B Mullick

Weifeng Ye

Sree Rangasai V Kesapragada

Avgerinos V Gelatos

Alexandros T Demos

Ho-yung David Hwang

David T Or

Nikolaos Bekiaris

Jong Mun Kim

Zhiyuan Wu

Vikash Banthia

Kevin Kashefi

Madhur Sachan

Srinivas Guggilla

Xi Cen

Chi-Chou Lin

Feiyue Ma

Nitin K Ingle

Abhijit Basu Mallick

David P Thompson

Anchuan Wang

Xianmin Tang

Paul F Ma

Soonam Park

Saurabh Garg

Huixiong Dai

Xinglong Chen

Jingmei Liang

Martin Jay Seamons

Kazuya Daito

Swaminathan T Srinivasan

Feng Chen

Jianxin Lei

Bhaskar Kumar

Keith Tatseun Wong

Jang-Gyoo Yang

Jonghoon Baek

Kevin Vincent Moraes

Lin Dong

Yongmei Chen

Mang-Mang Ling

Chia-Ling Kao

Wenting Hou

Mei Yin Chang

Ying Di Zhang

Srinivas Gandikota

Michael Wayne Stowell, Jr

Robert Jan Visser

Chi-I Lang

Kelvin Chan

Pramit Manna

Mandyam Sriram

Susmit Singha Roy

Joseph R Johnson

Zhenjiang Cui

Kang Sub Yim

Takehito Koshizawa

Shih Chung Chen

Raymond Hoiman Hung

Wen Xiao Chen

Qingjun Zhou

Bo Xie

El Mehdi Bazizi

Jie Zhou

Geetika Bajaj

Lu Chen

Yung-chen Lin

Xuesong Lu

Jingjing Liu

Jeremiah T Pender

Alexander Jansen

Tapash Chakraborty

Subhash Deshmukh

Jeremiah T P Pender

Guoqiang Jian

Yufei Hu

Jing Zhou

Angada Bangalore Sachid

Hua Ai

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

Fluorine-free tungsten ALD for dielectric selectivity improvement

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

Method of dielectric material fill and treatment

A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

Methods and apparatus for forming backside power rails

Methods of forming fully aligned vias connecting two metal lines extending in two directions are described. The fully aligned via is aligned with the first metal line and the second metal line along both directions. A third metal layer is patterned on a top of a second metal layer in electrical contact with a first metal layer. The patterned third metal layer is misaligned from the top of the second metal layer. The second metal layer is recessed to expose sides of the second metal layer and remove portions not aligned sides of the third metal layer.

Fully aligned subtractive processes and electronic devices therefrom

Methods for forming a nickel silicide material on a substrate are disclosed. The methods include depositing a first nickel silicide seed layer atop a substrate at a temperature of about 15° C. to about 27° C., annealing the first nickel silicide seed layer at a temperature of 400° C. or less such as over 350° C.; and depositing a second nickel silicide layer atop the first nickel silicide seed layer at a temperature of about 15° C. to about 27° C. to form the nickel silicide material.

Method of forming nickel silicide materials

Methods and apparatus for forming a reverse selective etch stop layer are disclosed. Some embodiments of the disclosure provide interconnects with lower resistance than methods which utilize non-selective (e.g., blanket) etch stop layers. Some embodiments of the disclosure utilize reverse selective etch stop layers within a subtractive etch scheme. Some embodiments of the disclosure selectively deposit the etch stop layer by passivating the surface of the metal material.

Reverse selective etch stop layer

Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

Subtractive metals and subtractive metal semiconductor structures

A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

Methods and devices for subtractive self-alignment

Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

Method of cleaning a structure and method of depositing a capping layer in a structure

Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Multi-step pre-clean for selective metal gap fill

Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of Oor chloride (Cl) while supplying nitrogen (N) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.

Methods and apparatus for processing a substrate

Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Methods for controllable metal and barrier-liner recess

Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

Selective tungsten deposition within trench structures

A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Method of forming interconnect for semiconductor device

Growing community of inventors

San Jose, CA, United States of America

He Ren