Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Hazuki Okabayashi

Tetsuya Tanaka

Ryuta Nakanishi

Tokuzo Kiyohara

Taketo Heishi

Hajime Ogawa

Takeshi Tanaka

Hideshi Nishida

Keisuke Kaneko

Shuji Miyasaka

Masaki Maeda

Masaitsu Nakajima

Takao Yamamoto

Tsuneyuki Suzuki

Masato Suzuki

Manabu Kuroda

Yoshihiro Koga

Masanori Henmi

Takatsugu Sawai

Hiroyuki Murata

Kiyokazu Fukuzaki

Hiroyuki Shigeta

A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.

Multiprocessor system for comparing execution order of tasks to a failure pattern

A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Parallel caches operating in exclusive address ranges

A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

Cache memory system, and control method therefor

A processor according to the present invention includes a decoding unit, an operation unitand others. When the decoding unitdecodes Instruction vcchk, the operation unitand the like judges whether vector condition flags VC&#x2dc;VC() of a condition flag register (CFR)are all zero or not, and (i) sets condition flags Cand Cof the condition flag register (CFR)to 1 and 0, respectively, when all of the vector condition flags VC&#x2dc;VCare zero, and (ii) sets the condition flags Cand Cto 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC&#x2dc;VCare stored in the condition flags C&#x2dc;C

Processor executing SIMD instructions

The cache memory in the present invention includes a C flag setting unitwhich adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unitwhich writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.

Cache memory and control method thereof

The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

N-way set associative cache memory and control method thereof

The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.

Cache memory and its controlling method

The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction 'jloop C,C:C,TAR,Ra', the processor (i) sets a conditional flag Cto 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag Cto a conditional flag C, moves the value of a conditional flag Cto the conditional flag C, and moves the value of the conditional flag Cto the conditional flags Cand C, (iii) adds &#x2212;1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags

A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction 'vxaddh Rc, Ra, Rb', an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Growing community of inventors

Osaka, Japan

Hazuki Okabayashi