Taiwan Semiconductor Manufacturing Comp. Ltd.

Haur-Ywh Chen

Fu-Liang Yang

Chenming Hu

Kuo-Nan Yang

Fang-Cheng Chen

Yi-Ling Chan

Hun-Jan Tao

Yuan-Hung Chiu

Hsien-Kuang Chiu

A method of fabricating a double gate, FINFET device structure in a silicon on insulator layer, in which the channel region formed in the SOI layer is defined with a narrowed, or necked shape, and wherein a composite insulator spacer is formed on the sides of the device structure, has been developed. A FINFET device structure shape is formed in an SOI layer via anisotropic RIE procedures, followed by a growth of a silicon dioxide gate insulator layer on the sides of the FINFET device structure shape. A gate structure is fabricated traversing the device structure and overlying the silicon dioxide gate insulator layer located on both sides of the narrowest portion of channel region. After formation of a source/drain region in wider, non-channel regions of the FINFET device structure shape, composite insulator spacers are formed on the sides of the FINFET shape and on the sides of the gate structure. Metal silicide is next formed on source/drain regions resulting in a FINFET device structure featuring a narrow channel region, and surrounded by composite insulator spacers located on the sides of the device structure.

Method of fabricating a necked FINFET device

A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

Method of fabricating a MOSFET device with metal containing gate structures

A new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a < > crystallographic orientation is bonded to the surface of a second silicon substrate having a < > crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a < > crystallographic orientation is bonded to the surface of a second silicon substrate having a < > crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.

Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement

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Kaohsiung, Taiwan

Haur-Ywh Chen