Taiwan Semiconductor Manufacturing Comp. Ltd.

Hau-Yi Hsiao

Cheng-Yuan Tsai

Kuo-Ming Wu

Cheng-Hsien Chou

Sheng-Chau Chen

Yung-Lung Lin

Chih-Hui Huang

Kuo-Hwa Tzeng

Ming-Che Lee

Ping-Tzu Chen

Chung-Yi Yu

Sheng-Chan Li

Chung-Jen Huang

Guanyu Luo

Che Wei Yang

Chun Liang Chen

Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Composite particulates for use as part of a supporting fill mixture in a semicondutor substrate stacking application

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Support structure to reinforce stacked semiconductor wafers

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Techniques for wafer stack processing

The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Semiconductor wafer seal ring having protrusion extending into trench in semiconductor substrate

Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

High reflectance isolation structure to increase image sensor performance

The present disclosure for wafer bonding, including forming an epitaxial layer on a top surface of a first wafer, forming a sacrificial layer over the epitaxial layer, trimming an edge of the first wafer, removing the sacrificial layer, forming an oxide layer over the top surface of the first wafer subsequent to removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer.

Method for wafer bonding including edge trimming

The present disclosure relates to a method and an associated process tool. The method includes generating electromagnetic radiation that is directed toward a perimeter of a pair of bonded workpieces and toward a radiation sensor that is arranged behind the perimeter of the pair of bonded workpieces. The electromagnetic radiation is scanned along a vertical axis. An intensity of the electromagnetic radiation that impinges on the radiation sensor is measured throughout the scanning. Measuring the intensity includes recording a plurality of intensity values of the electromagnetic radiation at a plurality of different positions along the vertical axis extending past top and bottom surfaces of the pair of bonded workpieces. A position of an interface between the pair of bonded workpieces is determined based on a maximum measured intensity value of the plurality of intensity values.

Process tool for analyzing bonded workpiece interface

A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

Protective wafer grooving structure for wafer thinning and methods of using the same

In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Damage prevention during wafer edge trimming

The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.

The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.

The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

Growing community of inventors

Chiayi, Taiwan

Hau-Yi Hsiao