Texas Instruments Corporation

National Semiconductor Corporation

Hau Thanh Nguyen

Anindya Poddar

Luu Thanh Nguyen

Ashok S Prabhu

Masamitsu Matsuura

Mutsumi Masumoto

Woochan Kim

Kengo Aoya

Viraj Ajit Patwardhan

Nikhil Vishwanath Kelkar

Vivek Kishorechand Arora

Yi Yan

Ken Pham

Makoto Yoshino

Rajeev Dinkar Joshi

Shahram Mostafazadeh

Makoto Shibuya

Genki Yano

Shoichi Iriguchi

Hiroyuki Sada

Dibyajat Mishra

Tomoko Noguchi

Roger William Clarke

Peter Deane

Ting-Ta Yen

William Paul Mazotti

Bruce Carlton Roberts

Nghia Thuc Tu

Mahmud Halim Chowdhury

Daiki Komatsu

Stephen Gee

John P Briant

Michael R Nelson

Janet E Townsend

Hideaki Matsunaga

Jie Mao

Ming Li

Nikhil K Kelkar

Edgar Dorotyao Balidoy

Kurt Edward Sincerbox

Masamitsu Matasuura

Aninyda Poddar

In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

Metal ribs in electromechanical devices

In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

Frame design in embedded die package

In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

Package for stress sensitive component and semiconductor device

A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

Semiconductor device package with thermal pad

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

Flip chip packaged devices with thermal pad

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Bump bond structure for enhanced electromigration performance

An electronic device () includes a substrate () and an integrated circuit () provided on the substrate () having a surface facing away from the substrate (). An insulating layer () extends over the substrate () and around the integrated circuit () to define an interface () between the insulating layer () and the integrated circuit (). An electrically conductive via () is provided on the surface of the integrated circuit (). An insulating material () extends over the via () and includes an opening () exposing a portion of the via (). A repassivation member () extends over the insulating layer () and has a surface () aligned with the interface (). An electrically conductive redistribution member () is electrically connected to the via () and extends over the repassivation member () into contact with the insulating layer ().

Fan-out electronic device

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Integrated circuit backside metallization

The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

Stress buffer layer in embedded package

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

Embedded die package multichip module

A dual leadframe () for semiconductor systems comprising a first leadframe () having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe () having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions () in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material () filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Semiconductor systems having dual leadframes

Growing community of inventors

San Jose, CA, United States of America

Hau Thanh Nguyen