Globalwafers Japan Co., Ltd.

Covalent Materials Corporation

Tohoku University

Haruo Sudo

Koji Araki

Susumu Maeda

Tatsuhiko Aoki

Koji Izunome

Takeshi Senda

Kazuhiko Kashima

Hiromichi Isogai

Eiji Toyoda

Kumiko Murayama

Hironori Banba

Kozo Nakamura

Koji Sueoka

Hideyuki Okamura

Tetsuo Endoh

Shoji Ikeda

Takashi Ishikawa

Akihiko Kobayashi

Etsuo Fukuda

Nobue Araki

Hiroyuki Saito

Yoichiro Mochizuki

Senlin Fu

Hisashi Matsumura

Kazuki Okabe

A silicon wafer is a Czochralski wafer formed of silicon. The wafer includes a bulk layer having an oxygen concentration of 0.5×10/cmor more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×10/cmor more.

Silicon wafer and method for producing silicon wafer

A processing temperature Tby a rapid thermal processing furnace is 1250&#xb0; C. or more and 1350&#xb0; C. or less, and a cooling rate Rfrom the processing temperature is in a range of 20&#xb0; C./s or more and 150&#xb0; C./s or less, and thermal processing is performed by adjusting the processing temperature Tand the cooling rate Rwithin a range between the upper limit P=0.00207T&#xb7;R&#x2212;2.52R+13.3 (Formula (A)) and the lower limit P=0.000548T&#xb7;R&#x2212;0.605R&#x2212;0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.

Thermal processing method for silicon wafer

An evaluation method of a silicon wafer allows non-destructive and non-contact inspection of a slip that affects the electrical properties of semiconductor devices, without being subjected to restrictions of the surface condition of silicon wafers or processing contents as much as possible. The evaluation method of a silicon wafer includes a step of section analysis where a surface of a single crystal silicon wafer after thermal processing is divided by equally-spaced lines into sections with an area of 1 mmor more and 25 mmor less and the existence of strain in each of the sections is determined based on a depolarization value of polarized infrared light, and a screening step where the wafer is evaluated as non-defective when the number of adjacent sections being determined to have strain by the section analysis step does not exceed a predetermined threshold value.

Evaluation method of silicon wafer

A silicon wafer includes a denuded zone which is a surface layer and of which the density of vacancy-oxygen complexes which are complexes of vacancies and oxygen is less than 1.0&#xd7;10/cm. An intermediate layer is disposed inwardly of the denuded zone so as to be adjacent to the denuded zone. The density of the vacancy-oxygen complexes in the intermediate layer increases gradually inwardly in the depth direction from the boundary with the denuded zone within a range of 1.0&#xd7;10/cmor over and less than 5.0&#xd7;10/cm. The intermediate layer has a depth determined corresponding to the depth of the denuded zone. A bulk layer is disposed inwardly of the intermediate layer so as to be adjacent to the intermediate layer. The density of the vacancy-oxygen complexes in the bulk layer is 5.0&#xd7;10/cmor over.

Silicon wafer

A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380&#xb0; C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [&#x3bc;m] which is calculated according to the below equations (1) to (3):[&#x3bc;m]=[&#x3bc;m]+[&#x3bc;m]&#x2003;&#x2003;(1);[&#x3bc;m]=(0.0031&#xd7;(said maximum temperature) [&#xb0; C.]&#x2212;3.1)&#xd7;6.4&#xd7;(cooling rate)&#x2212;[&#xb0; C./second]&#x2003;&#x2003;(2); and[&#x3bc;m]=/(solid solubility limit of oxygen) [atoms/cm]/(oxygen concentration in substrate) [atoms/cm]&#x2003;&#x2003;(3).

Silicon wafer and method for manufacturing the same

A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface regionwhich is a defect-free region and a bulk regionincluding void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Silicon wafer and method for heat-treating silicon wafer

A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T) of 1300&#xb0; C. or more, but less than 1380&#xb0; C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7&#xd7;10atoms/cmor more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.

Method of manufacturing single crystal silicon wafer from ingot grown by Czocharlski process with rapid heating/cooling process

The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to Tof 1300&#xb0; C. or higher and the melting point of silicon or lower, keeping the wafer at T, rapidly cooling the wafer to Tof 400-800&#xb0; C. and keeping the wafer at T; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T, rapidly heating the wafer from Tto Tof 1250&#xb0; C. or higher and the melting point of silicon or lower, keeping the wafer at Tand rapidly cooling the wafer.

Method for heat treating a silicon wafer

In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200&#xb0; C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

Method of heat treating silicon wafer

Growing community of inventors

Niigata, Japan

Haruo Sudo