Advanced Micro Devices Corporation

Globalfoundries Inc.

Hartmut Ruelke

Joerg Hohage

Minh Van Ngo

Kai Frohberg

Christof Streck

Katja Huy

Thomas Werner

Robert A Huertas

Jeremy Isaac Martin

Ulrich Mayer

Steven C Avanzino

Ralf Richter

Amit P Marathe

Volker Jaschke

Lothar Mergili

Sven Muehle

Lu You

Richard J Huang

Markus Lenski

Michael D Turner

Sey-Ping Sun

Volker Kahlert

Massud Aminpur

Homi E Nariman

Carsten Hartig

Frank Seliger

Gert Burbach

Karla Romero

Gotthard Jungnickel

Larry Zhao

Frank Mauersberger

Johannes Groschopf

Georg Sulzer

Frank Heinlein

Heinz-Juergen Voss

Michael Kiene

By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

Spacer for a gate electrode having tensile stress and a method of forming the same

By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.

Technique for forming a dielectric interlayer above a structure including closely spaced lines

The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress

A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components.

Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment

When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices.

Increased stability of a complex material stack in a semiconductor device by providing fluorine enriched interfaces

In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately 'encapsulated' by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

Non-insulating stressed material layers in a contact level of semiconductor devices

Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.

Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface

In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.

Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer

A new technique is disclosed in which a barrier/cap layer for a copper based metal line is formed by using a thermal-chemical treatment based on hydrogen with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma based deposition of silicon based dielectric barrier material. The thermal-chemical cleaning process is performed in the absence of any plasma ambient.

Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment

Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.

Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers

When forming dielectric materials of reduced dielectric constant in sophisticated metallization systems, the creation of defect particles on the dielectric material may be reduced during a plasma enhanced deposition process by inserting an inert plasma step after the actual deposition step.

Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step

A method for forming a silicon dioxide cap layer for a carbon hard mask layer for patterning of polysilicon line features having critical dimensions of 50 nm and less is provided. To this end, a low temperature plasma enhanced CVD process is used in which the deposition rate is maintained low to provide improved controllability of the layer thickness and, thus, of the optical characteristics of the silicon dioxide layer.

Method of forming a TEOS cap layer at low temperature and reduced deposition rate

A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness

A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, tensile stress is created in the channel region. The tensile stress leads to an increase of the electron mobility in the channel region.

Method of forming a field effect transistor comprising a stressed channel region

A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined compressive intrinsic stress having an absolute value of about 1 GPa or more. Due to this high intrinsic stress, the stressed layer exerts considerable elastic forces to the channel region of the transistor element. Thus, compressive stress is created in the channel region. The compressive stress leads to an increase of the mobility of holes in the channel region.

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Dresden, Germany

Hartmut Ruelke