International Business Machines Corporation

Other

Harry R Bickford

Linda C Matthew

Alfred Viehbeck

Michael J Palmer

Stephen L Tisdale

Voya Rista Markovich

Paul William Coteus

Martin J Goldberg

Elizabeth F Foster

Terrence Robert O'Toole

Timothy C Reiley

Donald G McBride

Peter J Duke

Daniel Mark Dreps

Paul Andrew Moskowitz

Robert H Dennard

Raymond R Horton

Gerard Vincent Kopcsay

Caroline A Kovac

Mark F Bregman

John C Zyzo

Warren Edward Maule

Lawrence Shungwei Mok

Thomas Mario Cipolla

Sung Kwon Kang

Michael John Brady

James Gardner Ryan

Daniel Peter Morris

Erick G Walton

Ismail C Noyan

Kurt R Grebe

Chin-An Chang

Peter G Ledermann

Robert Dominick Mirabella

Leonard T Olson

David Peter Pagnani

Ekkehard F Miersch

Paige A Poore

Arthur E Graham

Dennis A Canfield

Walter V Vilkelis

John Gow, Iii

Uh-Po E Tsou

William L Boland

Ismail C Novan

A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Variable voltage CMOS off-chip driver and receiver circuits

An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.

Variable voltage, variable impedance CMOS off-chip driver and receiver

A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.

Bidirectional off-chip driver with receiver bypass

A structure including a halogenated polymeric-containing layer. At least a portion of a surface of the halogenated polymeric-containing layer is electrochemically reduced. An electrically conductive pattern is provided over at least a portion of the electrochemically reduced portion of the halogenated polymeric-containing layer.

Structure including a partially electrochemically reduced halogenated

A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.

Method for conditioning halogenated polymeric materials and structures

A method of treating a halogenated polymeric-containing substrate including exposing at least portions of the halogenated polymeric-containing substrate to a composition containing a reducing agent and an aprotic solvent selected from the group consisting of nitriles, nitro compounds, amides, esters, carbonates, oxides, sulfo compounds and mixtures thereof. The solvent is free of ethers, amines, ammonia. The composition is prepared by reacting a metal with an organic compound selected from the group consisting of polyaryl compounds, aromatic carbonyl containing compounds, aromatic nitriles, and aromatic heterocyclic nitrogen containing compounds in a reaction solvent that does not react with the metal but permits reaction between the metal and the organic compound to thereby provide the reducing agent. The reducing agent is isolated from the reaction solvent to obtain a reaction product as a solid. The reaction product is added to the aprotic solvent. The treated substrate is contacted with a material to promote adhesion of the material to the treated surface.

A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Process of multilayer conductor chip packaging

A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Semiconductor chip packaging structure including a ground plane

A dielectric substrate is conditioned for subsequent electroless plating thereon by contacting with a catalytic metal salt and then with a reducing agent and with an electroless metal plating bath followed by contacting with a second catalytic metal salt. In addition, a dielectric substrate is conditioned for electroless plating thereon by obtaining a substrate of a dielectric material that contains metal particles therein and contacting with a catalytic metal salt.

Conditioning of a substrate for electroless plating thereon

Method and apparatus for fluxlessly solder bonding a solder mound to a solder wettable surface. A heated gas, preferably a reducing or non-reactive gas, is directed at a solid solder mound. Gas is heated to a temperature sufficient to melt solder mound. The heated gas is directed at the molten solder mound at a momentum sufficient to disperse an oxide layer at the surface of the molten solder mound. Dispersing the oxide layer permits the molten solder to wet the solder wettable surface. The molten solder is cooled to form a solder bond.

Method and apparatus for fluxless solder bonding

A semiconductor chip carrying integrated circuits has lead lines terminating in conductive terminal pads exposed to the exterior through openings in a passivation layer. The pads include pedestals or bumps extending up from them. Each of the pedestals includes a thin metallic adhesion layer deposited on the pad. A thick metallic layer of aluminum or an alloy of aluminum is deposited upon said thin metallic adhesion layer. The thick metallic layer includes at least one metal selected from the group consisting of aluminum, aluminum plus a small percentage of Cu, Ni, Si, or Fe. Several other alternative metals can be added to aluminum to form an alloy. The thick metallic layer forms the bulk of the height of the pedestal. An adhesion layer is deposited on the bump of aluminum composed of a thin film of titanium or chromium. A barrier layer is deposited on the adhesion layer composed of copper, nickel, platinum, palladium or cobalt. A noble metal consisting of gold, palladium, or platinum is deposited on the barrier layer. In a variation of the top surface, a thick cap of a reworkable bonding metal is deposited above the metallic bump as the top surface of said bump. The bump can be composed of a number of metals such as gold, copper, nickel and aluminum in this case with aluminum being preferred. In place of the adhesion and barrier metals one can employ a layer of titanium nitride deposited on said thick layer of metal.

Aluminum bump, reworkable bump, and titanium nitride structure for tab

Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Multilevel integrated circuit packaging structures

A TAB package comprises an elongated tape which has a plurality of sets of beam leads emplaced thereon and a plurality of electronic devices connected to the beam leads. At least a first beam lead of each set is connected to a common potential terminal on each device, and at least a second beam lead of each set is connected to a power terminal. A common potential bus is oriented along the elongated dimension of the tape and connects to the first beam leads, while a power bus is also oriented along the elongated dimension of the tape and is connected to the second beam leads. The application of power to the power bus and the simultaneous grounding of the common potential bus enables all electronic devices on the tape to be simultaneously energized and to be then subjected to an elevated temperature environment for static burn-in testing. To improve current conduction in the power and common potential buses, a tape comprising a non-conductive carrier and a pair of interposer/conductor tapes may be emplaced over the length of the tape bearing the chips. An additional spacer tape is then emplaced over the interposer tape and forces the interposer conductors into contact with the power and common potential buses.

Tab mounted chip burn-in apparatus

Growing community of inventors

Ossining, NY, United States of America

Harry R Bickford