Intel Corporation

Harry H Fujimoto

Qing Ma

Jin Hyung Lee

Krishna Seshan

Giang T Dao

Travis M Eiles

Siddhartha Das

Changhong Dai

Shiuh-Wuu Lee

Chun Mu

Eng T Gaw

Nelson N Tam

Qi De Qian

Jian Li

Quan Anh Tran

Steven N Towle

Chuanbin Pan

Rajiv Rastogi

John Carruthers

Ruben A Rodriguez

Sandra J Underwood

Henry Gaw

John E Evert

Lise Varner

An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

Isolation structure configurations for modifying stresses in semiconductor devices

Microelectronic packages including a microelectronic die disposed within a recess in a heat spreader and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the heat spreader to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die within the heat spreader. In another embodiment, a microelectronic die is disposed on a heat spreader which has a filler material disposed therearound and build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die and the filler material to form the microelectronic package, and methods for the fabrication of the same, including methods to align the microelectronic die on the heat spreader.

Die-in-heat spreader microelectronic package

An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon subtstrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

Silicon interposer and multi-chip-module (MCM) with through substrate vias

An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.

Integrated circuit guard ring structures

A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends vertically adjacent the microelectronic die active surface and vertically adjacent the encapsulation material surface.

Direct build-up layer on an encapsulated die package

An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon substrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

An enhanced heat dissipation device for a chip-on-flex packaged unit includes a flex circuit material attached to a front side of an integrated circuit die. The flex circuit material further attached to a bottom side of a printed circuit board having an opening to expose the flex circuit material. A top heat spreader thermally coupled to the flex circuit material through the opening in the printed circuit to dissipate heat from the front side of the integrated circuit die. The device further includes a bottom heat spreader, that is thermally coupled to back side of the integrated circuit die, to dissipate heat from the back side of the integrated circuit die. This enables the heat dissipation device to dissipate heat from both the front side and back side of the integrated circuit die, and thereby enhancing the heat dissipation for a given unit surface are of the integrated circuit die without increasing the volume of the heat dissipation device.

Heat spreader structures for enhanced heat removal from both sides of chip-on-flex packaged units

A chip-on-flex package which includes at least one moisture barrier layer to prevent metal corrosion and delamination of flex component layers. An exemplary microelectronic package includes a microelectronic die having an active surface and at least one side, wherein the microelectronic die active surface includes at least one contact. A flex component is attached by a first surface to the microelectronic die active surface. At least one conductive trace is disposed on a second surface of the flex component and extends through the flex component to contact at least one of the contacts. An encapsulation material is adjacent the microelectronic die side and a bottom surface of the flex component. A moisture barrier is disposed on the flex component and the conductive trace(s). A second moisture barrier may be disposed on the encapsulation material. A heat dissipation device may also be incorporated into the chip-on-flex package.

Structures and processes for fabricating moisture resistant chip-on-flex

Process for post exposure treatment of a latent image on a semiconductor wafer. After a deep ultraviolet (UV) photoresist has been exposed, the wafer, including the latent image in the attached photoresist, is maintained in an inert gas to protect the resist from the air atmosphere. Then the latent image is baked to stabilize the image.

Deep ultraviolet light photoresist processing

An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Interface between titanium and aluminum-alloy in metal stack for

Manufacturing techniques for forming waveguide channels and devices. A trench is formed in a cladding layer through an opening in a conductive layer. The trench is then filled with an active waveguide polymer and the conductive layer is patterned such that the active waveguide polymer may be poled. Also, a trench may be isotropically etched through a cladding layer to an underlying etch stop layer. The etch stop layer is thereafter removed from within the trench region to expose a previously formed, smooth, underlying cladding layer. Finally, a waveguide formed in a cladding layer, bounded in width by an overlying barrier layer, underlies a masking layer having a gap formed therein. Within the gap, a portion of the waveguide channel along with juxtaposing sections of the barrier layer are exposed. An etch is thereafter performed to remove the portion of the waveguide polymer in the waveguide channel bounded by both the masking layer and the barrier layer. Then an alternate type of waveguide polymer is formed in the void left behind by the etched waveguide polymer in the waveguide channel. Thus, a single waveguide channel having a plurality of waveguide polymers is formed.

Method of making integrated circuit waveguide

Method of forming an integrated circuit waveguide

A phase-shifted reticle with patterns proximate each other having inverted phases for the features and phase-shifting elements, and method of fabricating the reticle. Each of the patterns and inverted patterns are structurally identical with regard to the direction of phase shift, so that any focal shift due to phase error is in the same direction for all patterns. In a preferred embodiment, the structurally identical inverted reticle is used to form an array of closely spaced contact or via openings. For a first pattern on the reticle, the feature will be the 0.degree. phase and the phase-shifting rim surrounding that feature will be the 180.degree. phase. All patterns surrounding the first pattern have phase-shifting rims of the 0.degree. phase and features of the 180.degree. phase. In this way, each pattern can form below conventional resolution features in the resist. Additionally, there will not be exposure of the regions between the closely spaced features since radiation transmitted through the closely spaced phase-shifting rims of the two patterns is 180.degree. out of phase. Also, since each pattern is structurally identical, any focal shift due to phase error is in the same direction for all patterns, so that an acceptable depth of field is maintained for a substrate exposed with the reticle.

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Sunnyvale, CA, United States of America

Harry H Fujimoto