Qualcomm Incorporated

Harinatha Reddy Ramireddy

Ravindranath Doddi

Lekhya Pavani Godavarthi

Umamaheshwaran V

Afreen Haider

James Lionel Panian

Santhosh Reddy Akavaram

Ramacharan Sundararaman

Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.

Mechanism to improve the reliability of sideband in chiplets

Aspects relate to reduced training for main band chip module interconnection clock lines. In one example a method includes sending iterations of a first training pattern from a module of a first die to a module partner of a second die on a first main band clock line of a die-to-die connection, the die-to-die connection including a sideband, a main band comprising the first main band clock line, and at least one data line supported by at least the first main band clock line. An automatic result is received from the module partner through the sideband prior to completion of the iterations of the first training pattern, the automatic result indicating successfully receiving the training pattern. Data is communicated with the module partner through the main band using at least the first main band clock line in response to receiving the automatic result.

Reduced training for main band chip module interconnection clock lines

Aspects relate to an expanded data link width for a chip connection. In one example a sideband transmitter of a module of a first die is configured to send an expanded data link width enable request to a module partner through a sideband of a die-to-die connection to set an expanded data link width of a main band of the die-to-die connection. The expanded data link width includes data lines of the main band and redundant data lines of the main band reconfigured as data lines. A sideband receiver of the module is configured to receive an expanded data link width enable response from the module partner through the sideband to set the expanded data link width of the main band. A main band transmitter is configured to communicate data with the module partner through the main band using the expanded data link width.

Expanded data link width for main band chip module connection in alternate modes

Aspects relate to single clock lane operation for a main band of a die-to-die connection. In one aspect, a single clock mode is enabled. A method includes sending a switch to single clock mode request from a module of a first die to a module partner of a second die through a sideband to request to enable a single clock mode of a main band of a die-to-die connection that connects the first die module to the second die module partner. A switch to single clock mode response is received from the module partner through the sideband to enable the single clock mode and data is communicated with the module partner through the main band in the single clock mode using a functional clock.

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Hyderabad Telangana, India

Harinatha Reddy Ramireddy