Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Indian Institute of Science

Indian Institute of Technology Bombay

Intel Deutschland Gmbh

Harald Gossner

Mayank Shrivastava

Christian Cornelius Russ

Ramgopal Rao

Kai Esmark

Maryam Shojaei Baghini

Peter Baumgartner

Wolfgang Stadler

Richard Geiger

Thomas Schulz

Cornelius Christian Russ

Jens Schneider

Marko Radosavljevic

Han Wui Then

Sansaptak W Dasgupta

Domagoj Siprak

Martin Streibl

Stephan Leuschner

Uwe Hodel

Martin Wendel

Milova Paul

Wolfgang Soldner

Ram Asra

Hans-Joachim Barth

Sven Albers

Philipp Riess

Ulrich Glaser

Michael P Skinner

Gerhard Knoblinger

Richard Owen

David Johnsson

Georg Seidemann

Matthias Stecher

Thomas Wagner

Gunther Mackh

Gernot Langguth

Krzysztof Domanski

Wolfgang Molzer

Martin Ostermayr

Klaus Roeschlau

Georgios Panagopoulos

Angada Sachid

Ashish Pal

Reinhold Gaertner

Franz Zängl

Klaus Herold

Bernd Waidhas

Reinhard Mahnkopf

Werner Schwetlick

Michael Fulde

Teodora Ossiander

Benjamin Orr

Christian Mueller

Luis Giles

Michael Langenbuch

Benjamin J Orr

Jenia Elkind

Marin Streibl

Silke Bargstädt-Franke

Joachim Singer

B Sampath Kumar

Johannes Rauh

IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.

Buried power rails integrated with decoupling capacitance

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

III-N diodes with n-doped wells and capping layers

A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Semiconductor structure and method for forming a semiconductor structure

A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

Variable capacitance device with multiple two-dimensional electron gas (2DEG) layers

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride Schottky diode

A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

Group III-nitride silicon controlled rectifier

A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Group III-nitride antenna diode

A circuit for electrostatic discharge (ESD) protection for wide frequency range multi-band interfaces. The interface may be split into a plurality of signal paths. Each signal path may include an ESD protection circuit configured to shunt an ESD current on each signal path to either ground or supply voltage and a filter configured to block signals from other signal paths. The signal paths are connected to a common signal line such that the signals for the plurality of signal paths can be transported simultaneously. The plurality of signal paths may be a high frequency path and a low frequency path. The low frequency path may include an inductor connected in series and the high frequency path may include a capacitor or transformer connected in series. The ESD protection circuit on each signal path is placed behind the inductor, the capacitor or the transformer.

Circuit for electrostatic discharge protection for wide frequency range multi-band interfaces

The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.

Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device

SCRs are a must for ESD protection in low voltage&#x2014;high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.

FinFET SCR with SCR implant under anode and cathode junctions

The present disclosure relates to non-planar ESD protection devices. The present disclosure provides a device structure and method of fabricating the structure that is essentially immune to latch-up and possess high ESD robustness and reliability. In an aspect, the present disclosure provides a mixed silicidation and selective epitaxy (epi) FinFET processes for latch-up immunity together with ESD robustness, thereby allowing achievement of ESD efficient parasitic structures together with latch-up immune and reliable functional devices. The present disclosure provides a dual silicidation scheme where ESD protection element(s) have fins that are partially silicided, and functional devices have fins that are fully silicided. The present disclosure also provides a hybrid contact and junction profile scheme where ESD protection element(s) have fins that are partially silicided with or without deep junctions depending on their application, and functional devices have fins that are fully silicided with the silicide edge crossing the junction. On the other hand, a dual Epi scheme is implemented such that ESD protection elements have fins with Epi contact, and functional devices have fins that are fully silicided without Epi (raised S/D) contact.

Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

Tunnel field effect transistors

The present disclosure relates to a thermal management solution for ESD protection devices in advanced Fin- and/or Nanowire-based technology nodes, by employing localized nano heat sinks, which enable heat transport from local hot spots to surface of chip, which allows significant reduction in peak temperature for a given ESD current. In an aspect, the proposed semiconductor device can include at least one fin having a source and a drain disposed over a p-well or a n-well in a substrate; an electrically floating dummy metal gate disposed close to drain or hot spot over at least a portion of the at least one fin, and an electrical metal gate is disposed close to the source; and a nano-heat sink operatively coupled with the dummy metal gate and terminating at the surface of chip in which the semiconductor device is configured so as to enable transfer of heat received from the at least one fin through the dummy metal gate to the surface of the chip.

Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks

The present disclosure relates to a Silicon Controlled Rectifier (SCR) in non-planar technology to provide a robust ESD protection in System on Chip employing non-planar technologies. The disclosed SCR incorporates wire or fin shaped nanostructures extending from p-type tap to cathode, from the cathode to anode, and from the anode to n-type tap to provide parallel trigger paths to prevent problem of current crowding at the base emitter junction that limits efficient turn-on in conventional SCRs. The proposed structure helps in offering lower trigger and holding voltage, and therefore very high failure currents. The disclosed SCR has sub-3V trigger and holding voltage to provide an efficient and robust ESD protection in SOCs. The proposed device also offers three times better ESD robustness per unit area. Further the proposed SCR has no added capacitive loading and is compatible with standard process flow and design rules.

Low trigger and holding voltage silicon controlled rectifier (SCR) for non-planar technologies

Growing community of inventors

Riemerling, Germany

Harald Gossner