Shanghai Huali Microelectronics Corporation

Shanghai Huali Integrated Circuit Corporation

Shanghai Huali Integrated Circuit Mfg. Co., Ltd.

Haoyu Chen

Hua Shao

Zhi Tian

Qiwei Wang

Juanjuan Li

Zhen Gu

Lei Zhang

Xiaochuan Wang

Tao Hu

Xiaoliang Tang

Tianzhi Zhu

Guanqun Huang

Jinshuang Zhang

Feng Ji

Rong Zou

Xiang Peng

Naoki Tsuji

Shaokang Yao

The present application discloses an HV device, comprising: a gate dielectric layer formed in a first trench, a gate conductive material layer formed on the surface of the gate dielectric layer, and a second dielectric layer filling a second trench formed between a second side face of a drain shallow trench isolation and a first side face of the first trench. The depths of the first trench and the second trench are equal. The first trench and the second trench connect with each other to form an overall trench. Bottom surfaces of the second dielectric layer and the gate dielectric layer are flush with each other. A first side face of the gate conductive material layer extends to the surface of the second dielectric layer. The present application also discloses a method for manufacturing the HV device.

HV device and method for manufacturing same

The present application discloses a method for manufacturing a high-voltage metal gate device. After the deposition of a gate metal through a normal process, in CMP processes performed to the gate metal, firstly a first CMP process is performed to thin the gate metal to a certain thickness in advance, then a blocking dielectric layer is deposited, a large-area high-voltage gate region is opened through photolithography, and the blocking dielectric layer other than the blocking dielectric layer in the large-area high-voltage gate region is removed through etching. In a second CMP process performed to the gate metal, due to the blocking dielectric layer on the surface of the large-area gate metal in the high-voltage gate region, the polishing speed is slow, and CMP dishing will not be caused.

Method for manufacturing high-voltage metal gate device

The present application discloses a method for making an active area air gap, comprising: step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein each word line structure spans each field oxide and each active area; step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner; step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap; and step 4, removing the protective spacer.

Method for making active area air gap

The present application discloses a method for manufacturing a SONOS memory, including: providing a substrate, wherein a first transistor gate of the SONOS memory and a first layer used for forming a second transistor gate are formed on the substrate; forming a patterned second layer on the upper surface of the first layer, wherein the second layer exposes the first layer corresponding to the outer side of the second transistor gate; performing first etching on the first layer exposed by the second layer; removing the second layer; and performing second etching on the first layer to form the second transistor gate. The present application also discloses a SONOS memory. The present application can form a vertical structure outside a selective transistor and a storage transistor, thus forming a vertical side wall in the subsequent process, so as to improve the performance of the device.

SONOS memory and method for making the same

The disclosure discloses a global shutter CMOS image sensor, which adopts non-uniform storage diffusion region doping to reduce the junction leakage at storage points, so as to ensure that with the increase of the depth of photodiodes and the increase of pixels, all carriers in rows read subsequently can be transferred to storage diffusion regions, the loss of the carriers in the storage diffusion regions is not caused when a global shutter transistor is turned on, and the carriers can be completely transferred from the storage diffusion regions to floating diffusion regions through second transfer transistors even if the number of rows of pixel units increases during reading-out row by row. The disclosure further discloses a method for making the global shutter CMOS image sensor.

Global shutter CMOS image sensor and method for making the same

The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

Stack capacitor, a flash memory device and a manufacturing method thereof

The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.

Semiconductor structure of split gate flash memory cell

The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.

Semiconductor structure and the manufacturing method thereof

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped regionand an N-type lightly doped regionforming an anode formed on the upper part of an N-type well, a P-type heavily doped regionand an N-type heavily doped regionforming a cathode formed on the upper part of a P-type well, an active region of the N-type wellis between the N-type lightly doped regionand an interface of the N-type welland the P-type well, a STI is provided between the N-type heavily doped regionand the interface, the STI is adjacent to the N-type heavily doped region, and an active region of the P-type wellis provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

No-snapback silicon controlled rectifier and method for making the same

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped regionand an N-type heavily doped regionforming an anode formed on the upper part of an N-type well, a P-type heavily doped regionand an N-type heavily doped regionforming a cathode formed on the upper part of a P-type well, an active region of the N-type wellis between the N-type heavily doped regionand an interface of the N-type welland the P-type well, a STI is provided between the N-type heavily doped regionand the interface, the STI is adjacent to the N-type heavily doped region, and an active region of the P-type wellis provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

Silicon controlled rectifier and method for making the same

The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

Manufacturing method for a semiconductor device

The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

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Shanghai, China

Haoyu Chen