Texas Instruments Corporation

Haowen Bu

Rajesh B Khamankar

Malcolm John Bevan

Hiroaki Niimi

Husam N Alshareef

Douglas Ticknor Grider

Srinivasan Chakravarthi

Pr Chidambaram

Luigi Colombo

Amitabh Jain

Mark R Visokay

Jiong-Ping Lu

Shaofeng Yu

Shashank Sureshchandra Ekbote

Lindsey H Hall

Poornika Fernandes

Bhaskar Srinivasan

Brian Goodlin

Periannan Chidambaram

Mahalingam Nandakumar

Freidoon Mehrad

Antonio L P Rotondaro

Satyavolu Srinivas Papa Rao

Robert Kraft

Ping Jiang

Robert Christopher Bowen

Ting Yiu Tsui

Shaoping Tang

Clint Montgomery

Clinton L Montgomery

Juanita DeLoach

P R Chidambaram

Scott Robert Summerfelt

Amitava Chatterjee

Zhiqiang (Jeff) Wu

James Joseph Chambers

Manoj Mehrotra

Angelo Pinto

Manoj K Jain

Kaiping Liu

Guru Mathur

Asad Mahmood Haider

Stephanie Watts Butler

Yuanning Chen

Ajith Varghese

Song Zhao

Anand T Krishnan

John Paul Campbell

Borna J Obradovic

Douglas E Mercer

Scott Gregory Bushman

Che-Jen Hu

Jong Shik Yoon

Wayne A Bather

Shih Chang Chang

Brian Ashley Smith

Richard P Rouse

Eric H Warninghoff

Alan G Merriam

Bo-Yang Lin

Yen Lee

Poornika Gayathri Fernandes

Kanan Garg

Roger Charles McDermott

Sagnik Dey

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

IC with 3D metal-insulator-metal capacitor

In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V; and a capacitor second plate over the dielectric stack.

Precision capacitor

In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the upper silicon dioxide layer. The silicon oxy-nitride layer has an average index of refraction of 1.60 to 1.75 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. An upper plate layer is patterned to form the upper plate, leaving the lower silicon dioxide layer and at least half of the silicon oxy-nitride layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.

Capacitor with improved voltage coefficients

Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

System and method for mitigating oxide growth in a gate dielectric

A microelectronic device with a ferroelectric layer is formed using an MOCVD tool. A substrate is disposed on a susceptor heated to 600&#xb0; C. to 650&#xb0; C. A first carrier gas is flowed into a manifold to combine with a plurality of metal organic precursors. The first carrier gas, the metal organic precursors, and a second carrier gas, are flowed through a vaporizer into a chamber of the MOCVD tool, over the substrate. A ratio of a flow rate of the first carrier gas to a flow rate of the metal organic precursors is 250 sccm/milliliter/minute to 500 sccm/milliliter/minute. A ratio of a flow rate of the second carrier gas to a flow rate of the metal organic precursors is 700 sccm/milliliter/minute to 1500 sccm/milliliter/minute. An oxidizing gas is flowed into the chamber over the substrate. The metal organic precursors and the oxidizing gas react to form the ferroelectric layer.

Process to enable ferroelectric layers on large area substrates

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