Globalfoundries Inc.

Hao Zhang

Judson Robert Holt

Timothy James McArdle

Scott Beasor

George Robert Mulfinger

Dina Triyoso

Lakshmanan H Vanamurthy

Sven Schmidbauer

Robert Binder

Elke Erben

A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.

Self-aligned sacrificial epitaxial capping for trench silicide

A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Methods for fabricating integrated circuits with narrow, metal filled openings

Disclosed herein are various methods of forming replacement gate structures for semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity for a replacement gate structure, forming a gate insulation layer in the gate cavity and forming a layer of metal above the gate insulation layer. In this example, the method also includes forming a patterned etch mask layer above the metal layer that exposes substantially vertically oriented portions of the metal layer within the cavity and covers a substantially horizontally oriented portion of the metal layer within the cavity, performing an etching process through the patterned etch mask layer to reduce a thickness of the exposed substantially vertically oriented portions of the metal layer and removing the patterned etch mask layer.

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Clifton Park, NY, United States of America

Hao Zhang