Marvell Asia Pte., Ltd.

Globalfoundries U.S. Inc.

Hao Pu

Wei Zhao

Xiaoli Hu

Igor Arsovski

George Maria Braceras

Qing Li

Shuangdi Zhao

Yuzheng Jin

A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.

Multi-port high performance memory

A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.

Write scheme for a static random access memory (SRAM)

Growing community of inventors

Shanghai, China

Hao Pu