Vanguard International Semiconductor Corporation

Winbond Electronics Corporation

Hao-Chieh Liu

Erik S Jeng

Bi-Ling Chen

Tzu-Shih Yen

Wan-Yih Lien

Fu-Liang Yang

Hung-Yi Luo

A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen. There is then formed a plasma by supplying high frequency electrical energy to the electrodes within the reactor chamber to bring about a plasma activated reactive gas etching environment, where the conditions may be selected to optimize the desired etch rate and etch rate selectivity.

Etching process

A method for forming a plug or damascene trench on a semiconductor device includes the following steps: depositing a dielectric layer consisting of hydrogen silsesquioxane (HSQ) on the semiconductor device, depositing a mask layer consisting of a hard mask material on the dielectric layer, removing a portion of the mask layer and defining the remaining portion of the mask layer as a hard mask, curing the portion of the dielectric layer not covered with the hard mask by e-beam; removing the portion of the dielectric layer not being cured by e-beam with a wet etch process to create an opening in the dielectric layer, wherein the wet etch rate of the portion of the dielectric layer being e-beam cured is significantly lower than that of the portion of the dielectric layer not being e-beam cured, and filling the opening in the dielectric layer with a kind of metal material or polysilicon.

Method for forming a plug or damascene trench on a semiconductor device

A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

Method for forming self-aligned contacts using a hard mask

The present invention includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is then formed over the semiconductor substrate, the first dielectric layer, and the spacer, followed by forming a photoresist layer on the first silicon oxide layer. A predetermined thickness of the first silicon oxide layer is removed by using the photoresist layer as a mask, and a polymer layer is then formed on the photoresist layer and the first silicon oxide layer. The polymer layer is anisotropically etched back to form a polymer spacer on sidewalls of the photoresist layer and the first silicon oxide layer. The first silicon oxide layer is then anisotropically etched back by using the polymer spacer as a mask to expose surface of the semiconductor substrate, wherein the spacer and the first dielectric layer are used for facilitating self-aligned etching. A second conductive layer is formed over the semiconductor substrate, surface of the second silicon oxide layer being exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, a portion of the second silicon oxide layer is patterned to expose a portion of the second conductive layer, thereby forming the contact hole in the second oxide layer.

Method of forming a contact hole in a semiconductor device

A method for forming multi-level contact holes in a semiconductor structure is disclosed. The semiconductor structure includes a dielectric layer overlying a silicon substrate, a silicon nitride layer within the dielectric layer, the silicon nitride layer overlying a first conductive layer, a silicon oxynitride layer within the dielectric layer, the silicon oxynitride layer overlying a second conductive layer, and a plate poly layer. The method comprises: using a first etching step to etch through the dielectric layer to reach the silicon nitride layer as well as reach the silicon oxynitride layer, the first etching step using a combination of a first gas mixture and a first gas, the first gas mixture comprising a combination of N.sub.2, CO and Ar. The first gas includes C.sub.4 F.sub.8, CH.sub.3 F and O.sub.2, the flow rate ratio of the first gas C.sub.4 F.sub.8 /CH.sub.3 F/O.sub.2 is about 6:1:3. The flow rate of each component of the first gas mixture is that, the flow rate of N.sub.2 is about 0-20 sccm, the flow rate of CO is about 0-200 sccm, and the flow rate of Ar is about 100-600 sccm. In addition, the flow rate of each component of the first gas is that, the flow rate of C.sub.4 F.sub.8 is about 8-40 sccm, the flow rate of CH.sub.3 F is about 1-7 sccm, and the flow rate of O.sub.2 is about 0-20 sccm. Then using a second etching step to etch through the silicon nitride layer to reach the first conductive layer, the second etching step also etching through the silicon oxynitride layer to reach the second conductive layer. The second etching step uses a combination of the first gas mixture and a second gas, the second gas comprising CH.sub.3 F of the flow rate of about 3-14 sccm.

Method for forming multi-level contacts using a H-containing

A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

Method for forming multi-level contacts

A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.

Method for simultaneously fabricating capacitor structures, for giga-bit

A new method of forming a contact opening through multiple layers is described. A first dielectric layer is deposited over semiconductor device structures formed in and on a semiconductor substrate. A patterned conductor layer is formed overlying the first dielectric layer and covered with a second dielectric layer. A retardation layer is deposited overlying the second dielectric layer wherein the retardation layer has a first etch rate. A third dielectric layer is deposited overlying the retardation layer wherein the third dielectric layer has a second etch rate higher than the first etch rate. A mask is formed over the third dielectric layer having an opening of a first size above one of the semiconductor device structures to be electrically contacted. A contact opening is etched through the first, second, and third dielectric layers and the retardation layer not covered by the mask to the structure to be contacted wherein the contact opening through the third dielectric layer is of the first size and wherein the retardation layer is etched at an angle because of the first etch rate slower than the second etch rate and wherein the contact opening through the second and first dielectric layers underlying the angled retardation layer has a second size smaller than the first size thereby completing the formation of a contact opening in the fabrication of an integrated circuit device.

Method for fabricating reduced contacts using retardation layers

A method for etching dielectric layers is disclosed. A first etch of the dielectric layers is performed with a gas chemistry comprising C.sub.4 F.sub.8 flowing at about 10 sccm to about 25 sccm and CH.sub.3 F flowing at about 5 sccm to about 20 sccm. A second etch of the dielectric layers is performed with the gas chemistry and flow rates of gases which are about 10% to about 40% greater than the flow rates of gases in the first etch.

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Taipei, Taiwan

Hao-Chieh Liu