Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Hao-Cheng Hou

Tsung-Ding Wang

Chien-Hsun Lee

Jung-Wei Cheng

Jung Wei Cheng

Chung-Shi Liu

Hung-Jen Lin

Ming-Che Liu

Chun-Chih Chuang

Jiun Yi Wu

Yu-min Liang

Hsin-Yu Pan

Yu-Min Liang

Hai-Ming Chen

Chen-Hua Douglas Yu

Hung-Jui Kuo

Chih-Wei Lin

Wei-Yu Chen

Ching-Hua Hsieh

Yu-Hsiang Hu

Yu-Feng Chen

Meng-Tse Chen

Sih-Hao Liao

Wei-Chih Chen

Chin-Liang Chen

Chi-Yang Yu

Chih-Huang Lai

Li-Wei Chou

Ming-Chung Sung

Yen-Fu Su

Mirng-Ji Lii

Sao-Ling Chiu

Chien-Hsun Chen

Yi-Yang Lei

Ping-Kang Huang

Chao-Chien Chiang

Meng-Shian Lin

Jung-Wei Liao

A semiconductor package includes a first integrated circuit, a first conductive via, a second conductive via, a second integrated circuit, a third conductive via and an encapsulant. The first conductive via is disposed in a first passivation layer over the first integrated circuit. The second conductive via is disposed in a second passivation layer over the first passivation layer. The second conductive via is electrically connected to the first conductive via. The third conductive via is disposed over the second integrated circuit, wherein a surface of the third conductive via is substantially coplanar with a surface of the third conductive via. The encapsulant encapsulates the first integrated circuit, the first passivation layer, the second passivation layer, the second integrated circuit and the third conductive via.

Semiconductor packages and method of manufacturing the same

A laminated structure and the manufacturing methods thereof are provided. The structure includes an interconnect substrate having a first surface and a second surface opposite to the first surface, an insulating encapsulant laterally wrapping the interconnect substrate, and a redistribution structure disposed on the first surface of the interconnect substrate and electrically connected with the interconnect substrate. The redistribution structure has a third surface facing the first surface and a fourth surface opposite to the third surface. The redistribution structure includes first pads, second pads located beside the first pads, and protective patterns disposed on the first pads and covering the first pads. The first pads include pad portions protruded from the fourth surface and the protective patterns are in contact with sidewalls and top surfaces of the pad portions of the first pads.

Laminated structure with pads and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.

Package structure and forming method thereof

A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.

Semiconductor package and methods of fabricating a semiconductor package

A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Semiconductor package

A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.

Probe card substrate, substrate structure and method of fabricating the same

An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Semiconductor packages and methods of forming same

A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Package structure comprising buffer layer for reducing thermal stress and method of forming the same

A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.

Semiconductor package with through vias and stacked redistribution layers and manufacturing method thereof

A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.

Semiconductor package having molded die and semiconductor die and manufacturing method thereof

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Connector formation methods and packaged semiconductor devices

A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

Semiconductor package including dies having high-modulus dielectric layer and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.

Semiconductor package and manufacturing method thereof

Redistribution structures in semiconductor packages and methods of forming same

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Hsinchu, Taiwan

Hao-Cheng Hou