Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Chang Chun Petrochemical Co., Ltd.

Chang Chun Plastics Co., Ltd.

Far Eastone Telecommunications Co., Ltd.

Hao Chen

Mill-Jer Wang

Hung-Chih Lin

Ching-Nen Peng

Kuo-Chuan Liu

Chewn-Pu Jou

Huan-Neng Chen

Feng Wei Kuo

Mincent Lee

Ming-Chieh Liu

Sen-Kuei Hsu

Kuang-Kai Yen

Tsung-Hsiung Lee

Min-Jer Wang

Chung-Han Huang

Chuan-Ching Wang

Chih-Chia Chen

Chun-Hsing Chen

Wen-Feng Liao

Ching Nen Peng

Shao-Chun Chiu

Chen-Shien Chen

Wen-Yi Lin

Ching-Fang Chen

Chien-Chen Li

Chung-Sung Tan

Chun-Cheng Chen

Wei-Hsun Lin

Tang-Jung Chiu

Chung-Sheng Yuan

Chi-Che Wu

Meng-lin Chung

Hua-Pei Chiang

Wei-Han Hsiao

Chyi-Dar Jang

Tsung-Hsiung Li

Tsung-Jen Wang

Chuan-Hsiang Sun

Shang-Ju Lee

Che-Yu Liao

Chun-Chieh Kuo

Chi-Hung Lin

Chi-En Chien

Chen-Hsiang Hsu

Wen-Wen Hsieh

Chen-Hung Tien

Chang Chia How

Kuang Kai Yen

A system and a method for automatically adjusting a beam direction of a reflector are provided. The system includes: a reflector for reflecting, refracting, or transmitting incident waves of network signals to a specified area; a database, storing optimized setting combinations for specified areas that include an altitude of the reflector and angles thereof with respect to the specified area, making signals of the specified area have maximum intensity; a communication module, receiving a trigger signal; a computing and processing module, retrieving from the optimized setting combination for the specified area according to the area name of the trigger signal; and a control module, adjusting the altitude and angles of the reflector according to the optimized setting combination. The disclosure can automatically detect a specified area needing network service and automatically adjust the reflector for signal intensity enhancement.

System and method for automatically adjusting beam direction of reflector

A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.

Method for forming probe head structure

A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.

Testing device for integrated circuit package

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Testing module and testing method using the same

A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

Test circuit and method

A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.

Testing device and method for integrated circuit package

A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

Testing holders for chip unit and die package

An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.

Composite integrated circuits and methods for wireless interactions therewith

A testing system includes a load board that includes a first circuit board, a first external connector attached to the first circuit board, and a thermal module configured to hold a system-on-wafer structure including a connector and a socket, a connector structure including a second circuit board, wherein the second circuit board is electrically connected to the first external connector, and a second external connector configured to connect to the connector of the system-on-wafer structure, and a test structure configured to connect to the socket of the system-on-wafer structure, the test structure including a third circuit board and pins, wherein adjacent pairs of pins of the test structure are electrically coupled through the third circuit board to form a continuous conductive path extending alternately between the system-on-wafer structure and the adjacent pairs of pins of the test structure.

System and method for semiconductor device testing

Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Alignment testing for tiered semiconductor structure

A semiconductor device includes a circuit board, a semiconductor package, and a contact interface. The semiconductor package is mounted on the circuit board. The semiconductor package includes a plurality of conductive bumps with a first pitch. The contact interface is electrically connected to the circuit board. The contact interface includes a plurality of first contact pads with a second pitch substantially the same as the first pitch. The first contact pads are separated from the conductive bumps.

Universal test mechanism for semiconductor device

Growing community of inventors

Taipei, Taiwan

Hao Chen