Siemens Aktiengesellschaft

Infineon Technologies Ag

Qimonda Ag

Hans Reisinger

Reinhard J Stengl

Hermann Wendt

Volker Lehmann

Josef Willer

Martin Franosch

Franz Hofmann

Gerrit Lange

Wolfgang Krautschneider

Herbert Sch&auml;fer

Thomas Peter Haneder

Harald Bachhofer

Wolfgang H&ouml;nlein

Ulrike Gr&uuml;ning

Helmut Klose

Thomas Mikolajick

Corvin Liaw

Herbert Schaefer

Stefan Ottow

Ulrike Gruning

Bernhard Sell

Lothar Risch

Emmerich Bertagnolli

Thomas Aichinger

Dietrich Widmann

Paul-Werner Von Basse

Herbert Schäfer

Matthias Ilg

Gerhard Beitel

Wolfgang Hoenlein

Dirk Schumann

Wolfgang Hönlein

Andreas Spitzer

Barbara Hasler

Andre Kabakow

Paul Werner Von Basse

Bernd Gobel

Stephan Schlamminger

Karl-Heinz Tietgen

Thomas Bohm

Reinhard Stengel

Paul-Werner Basse

Maximilian Wolfgang Feil

A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.

Semiconductor device having an optical device degradation sensor

To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

Charge-trapping memory device and methods for operating and manufacturing the cell

The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.

Charge-trapping memory device including high permittivity strips

The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

Memory device for storing electrical charge and method for fabricating the same

A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly covers the surface of the pores.

Reactor configuration and method for producing it

A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor

A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.

Memory cell arrangement

A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Ferroelectric transistor and memory cell configuration with the ferroelectric transistor

An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

Optical structure and method for producing the same

A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the pores. The entire surface of the substrate is covered with a mask layer that is structured photolithographically on the rear of the substrate. The bottoms of the pores in the second region are etched clear, preferably using KOH.

Perforated work piece, and method for producing it

A DRAM capacitor is described that contains a BaSrTiO (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

DRAM memory capacitor having three-layer dielectric, and method for its production

A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Storage capacitor for a DRAM

A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.

Method for fabricating a memory cell configuration

A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

Memory cell configuration with capacitor on opposite surface of substrate and method for fabricating the same

A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

Capacitor for semiconductor configuration and method for fabricating a dielectric layer therefor

Growing community of inventors

Grünwald, Germany

Hans Reisinger