Globalfoundries Inc.

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Infineon Technologies Dresden Gmbh & Co . Kg

Hans-Juergen Thees

Peter Baars

Stephan Kronholz

Anton Mauder

Peter Javorka

Elliot John Smith

Martin Mazur

Olaf Storbeck

Marc Probst

Tom Richter

Stefan Loesch

Kai Frohberg

Sven Beyer

Roman Baburske

Markus Lenski

Maciej Wiatr

Alexander Philippou

Peter Moll

Dominic Thurmer

Joerg Radecker

Heike Scholz

Joerg Schmid

Dietmar Henke

Steffen Laufer

Alim Karmous

Thorsten Arnold

Henke Dietmar

Ilaria Imperiale

A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

Voltage-controlled switching device with channel region

A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa.

Power semiconductor device having a control cell for controlling a load current

A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions.

Power semiconductor device including first and second trench structures

A power semiconductor device includes: a semiconductor body with a drift region; a plurality of trenches, wherein two adjacent trenches laterally confine a mesa of the semiconductor body. Each trench extends along a vertical direction and includes a trench electrode, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length amounting to at least five times the trench width. The device further includes: a semiconductor body region of a second conductivity type in the mesa; a source region in the mesa; an insulation layer above and/or on the source region; a contact plug that extends at least from an upper surface of the insulation layer along the vertical direction so as to contact both the source region and the semiconductor body region.

Mesa contact for a power semiconductor device and method of producing a power semiconductor device

A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.

Method of processing a power semiconductor device

An embodiment of a semiconductor device includes a semiconductor mesa in an active device area. The semiconductor mesa includes source regions arranged along a longitudinal direction of the semiconductor mesa and separated from one another along the longitudinal direction. The semiconductor device further includes an electrode trench structure including a dielectric and an electrode. The electrode trench structure adjoins a side of the semiconductor mesa. The semiconductor device further includes an isolation trench structure filled with one or more insulating materials. The isolation trench structure extends through the semiconductor mesa and into or through the electrode trench structure along a first lateral direction.

Semiconductor device including electrode trench structure and isolation trench structure and manufacturing method therefore

A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.

Semiconductor device with novel spacer structures having novel configurations

An auxiliary layer is formed above a semiconductor body surface of a semiconductor body, the auxiliary layer being coupled to the semiconductor body and having an auxiliary layer surface. Trenches extend from the auxiliary layer surface along a vertical direction through the auxiliary layer into the semiconductor body, wherein two facing trench sidewalls of two adjacent trenches laterally confine a mesa region of the semiconductor body along a first lateral direction, each adjacent trench including a trench section protruding out of the semiconductor body surface. The trenches are filled with a trench filler material which is planarized to expose the auxiliary layer. The auxiliary layer is removed to least partially while maintaining the protruding trench sections. The mesa region is subjected to an implantation tilted by an angle of at least 10&#xb0;, the protruding trench sections of the adjacent trenches serving at least partially as a mask during the implantation.

Power semiconductor device with self-aligned source region

A device including an SOI substrate and an isolation structure positioned at least partially in a trench that extends through a buried insulation layer and into a semiconductor bulk substrate of the SOI substrate is disclosed. The isolation structure includes a first dielectric layer positioned in a lower portion of the trench, a first material layer positioned above the first dielectric layer, the first material layer having a material different from a material of the first dielectric layer, and a second dielectric layer positioned above the first material layer, the second dielectric layer having a material different from the material of the first material layer.

Semiconductor device with interconnect to source/drain

A method of manufacturing a semiconductor device is provided including providing an SOI substrate comprising a semiconductor bulk substrate, a buried insulation layer and a semiconductor layer, forming a shallow trench isolation in the SOI substrate, forming a FET in and over the SOI substrate, and forming a contact to a source or drain region of the FET that is positioned adjacent to the source or drain region, wherein forming the shallow trench isolation includes forming a trench in the SOI substrate, filling a lower portion of the trench with a first dielectric layer, forming a buffer layer over the first dielectric material layer, the buffer layer having a material different from a material of the first dielectric layer, and forming a second dielectric layer over the buffer layer and of a material different from the material of the buffer layer.

The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.

Cap removal for gate electrode structures with reduced complexity

A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate structure having a gate insulation layer over the semiconductor layer and at least one P-type metal-oxide semiconductor gate structure being a PZG gate structure having a gate insulation layer over the semiconductor layer, the NZG and PZG gate structures being electrically separated from each other.

Air gap spacer implant for NZG reliability fix

The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

Method of forming a semiconductor device structure and semiconductor device structure

A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.

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The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

Growing community of inventors

Dresden, Germany

Hans-Juergen Thees