Siemens Aktiengesellschaft

Hans-Juergen Mattausch

Gerd Neuendorf

Doris Schmitt-Landsiedel

Hans-Joerg Pfleiderer

Maria Wurm

Bernhard Hoppe

Matthias Schoebinger

Fred Matthiesen

Klaus Althoff

A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.

Hierarchically constructed memory having static memory cells

Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

Static memory cell

A read amplifier formed of a load component (L), a differential amplifier component (DIFF), a compensation transistor (N6), a switching transistor (P1) connected between a supply voltage (V.sub.DD) and the load component (L). The pre-loading potential of the read amplifier at its outputs LA, LA is about 2.5 volts. During the pre-loading phase, the two supply voltages (V.sub.DD, V.sub.22 =ground) are disconnected and the pre-loading potential is established by compensation of capacitances at the outputs LA, LA which results in an improved read amplifier.

Read amplifier for static memories in CMOS technology

An arrangement for DPCM coding with high data rate. In a DPCM coder, wherein respective prediction values (s) are subtracted from digitized picture element signals (s), the difference signals that result represent the prediction error .DELTA. supplied to a circuit element for cutputting a quantization error (11) pertaining to a difference signal. In a following adder, quantization errors (q) are added to the prediction errors (.DELTA.), whereby the quantized prediction error (.DELTA.q) can be taken at the output of the following adder. For forming the reconstructed picture element signal (s.sub.R), the quantization error (q) is added to the current picture element signal (s) in a first adder and is supplied to a first subtraction means via a predictor. In an embodiment of the circuit, a DPCM structure that has a shortest possible critical path for a DPCM structure that is composed of a quantizer, of an addition and of a register can be produced by dividing the predictor upon insertion or removal of individual registers.

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Brunnthal-Faistenhaar, Germany

Hans-Juergen Mattausch