International Business Machines Corporation

Hans-Joachim Trumpp

Reinhold Muhl

Otto Koblinger

Johann Greschner

Klaus Meissner

Werner Zapka

Uwe Behringer

Dieter Hagmann

Wolfgang Euen

Eva Horner

Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad. On top of the planarized topology, the second layer of the double-layer insulation is applied, and vias are opened in the layer by a plurality of dry-etching steps. The second metalliation pattern is formed on this second layer. Then, another double-layer insulation is applied on top of the second metallization pattern, the first layer being an inorganic and the second layer an organic layer. After opening vias in the layers of this double-layer insulation by contour-etching, a third metallization pattern is applied. Optionally, a fourth metallization pattern can be formed on the integrated circuit structure.

Method for producing an integrated circuit structure with a dense

In the course of the process for making masks with structures in the submicrometer range, initially structures of photoresist or polymer material with horizontal and substantially vertical sidewalls are produced on a silicon substrate covered with an oxide layer. This is followed by a layer of silicon nitride which is deposited by LPCVD. The resultant structure is planarized with a photoresist which is etched back until the start of the vertical edges of the sidewall coating formed by the nitride layer is bared on the photoresist structures. In a photolithographic step, a trimming mask is produced on the surface of the nitride layer and the planarizing resist. The bared regions of the nitride layer are then removed by isotropic etching. The dimensions A-B of the openings defined after removal of the nitride layer from the vertical surfaces of the photoresist structures are transferred to the oxide layer by anisotropic etching. Concurrently with these structures of minimum line width, registration marks are generated which allow the adjustment necessary for a further photolithographic step to be carried out with maximum accuracy. After removal of the trimming mask, the planarizing resist, the photoresist structures and the remainder of the nitride layer, structures with coarser line widths are defined in a further photolithographic step, which are also transferred to the oxide layer. Using the oxide layer as a mask, trenches of the desired depth are produced in the silicon substrate by anisotropic etching. The mask is thinned by anisotropic etching, and the oxide layers are removed from the front and the back side by wet etching.

Process for making masks with structures in the submicron range

Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle &lt; about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount. The improved method of the invention provides for the plasma nitride mask to be removed first, using, if necessary a facetting step in oxygen to increase the positive angle in the mask structure, and then for the latter structure to be laterally etched in oxygen to reduce its dimensions by the desired amount. As the angle in the mask is &lt; about 90.degree., the parameters for lateral etching may be chosen such that the etch process is largely anisotropic and, thus, accurately and readily determinable. As a result, the absolute amount of lateral etching may be accurately adjusted during the etch period. As shading plasma nitride is removed before lateral etching, the influence of neighboring structures on lateral etching is largely reduced. The mask thus produced is used to etch in the polysilicon layer structures whose angles ensure a good definition of the spacers to be produced in the subsequent process steps and of ion implantation, which both determine the effective channel length of field-effect transistors.

Method of producing integrated semiconductor structures comprising

A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C. during which controllable quantities of the polycrystalline silicon are consumed. After removal of the thermally grown oxide, polycrystalline silicon portions are obtained with length and thickness dimensions reduced by a desired amount. If polycrystalline silicon portions are to be reduced only in length, the horizontal surfaces of these portions are protected during oxidation by a cap. The cap may include a several nm thick silicon nitride layer which is arranged on a silicon dioxide stress-relieve layer. The method is particularly useful in forming a submicrometer length gate electrode of a field effect transistor.

Method for fabricating a semiconductor integrated circuit structure

A method of making via holes in a double-layer insulation of nitride and polyimide. The via holes are made with one photomask only by applying a photoresist process with double exposure, and a multi-step dry etching process. The double exposure, which includes an image-wise exposure followed by blanket irradiation, achieves an edge angle in the photoresist between approx. 60.degree. and 70.degree., depending on the exposure time ratios. This angle is transferred into the polyimide layer in a dry etching process. In a first etching step with CF.sub.4 as etching gas the greater part of the polyimide is removed. For removing the residual polyimide in the via holes there now follows an etching step in O.sub.2. Etch bias is thus kept on a very low level. The nitride layer is then etched with CF.sub.4 as etching gas, with the etching process being executed in two steps, each followed by an etching step in O.sub.2 for laterally shifting the photoresist and the polyimide via the resist angle. By softening the step height a softer profile of the via holes is ensured, which permits very good covering by a second layer of metallurgy.

Process of making via holes in a double-layer insulation

A method of making trenches having substantially vertical sidewalls in a silicon substrate using a three level mask comprising a thick photoresist layer, a silicon nitride layer and a thin photoresist layer. Openings are formed in the thin photoresist layer and silicon nitride layer by reactive ion etching in CF.sub.4. The openings are continued through the thick photoresist by etching in an atmosphere containing oxygen. The exposed surface of the silicon substrate is then etched in a CF.sub.4 atmosphere containing a low concentration of fluorine. Also disclosed is a method of making an electron beam transmission mask wherein the openings are made using the three level mask and reactive ion etching of silicon using the etching technique of the invention.

Method of making trenches with substantially vertical sidewalls in

Following the method of making structures with dimensions in the submicrometer range, structures of a polymeric layer with horizontal and substantially vertical surfaces are first made on a substrate. Thereupon, a silicon nitride or oxide layer is plasma deposited. This layer is subjected to reactive ion etching methods in such a manner that its horizontal regions and the polymeric structures are removed, with merely the narrow regions of the silicon nitride or oxide layer that had originally been arranged adjacent the vertical surfaces of the polymeric structures remaining. In the case of positive lithography, the silicon nitride or oxide walls are converted into a mask with the same dimensions but consisting of a different mask material. In the case of negative lithography the silicon nitride or oxide walls are converted in a mask reversal process into openings in a mask material layer through which by means of reactive ion etching vertical trenches approximately 0.5 .mu.m deep can be etched in the silicon substrate. The trenches are filled by thermal oxidation or with a synthetic material as e.g. polyimide. The method as disclosed by the invention can also be applied to other processes than recessed isolation in semiconductor technology.

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Filderstadt, Germany

Hans-Joachim Trumpp