Infineon Technologies Ag

Infineon Technologies Austria Ag

Siemens Aktiengesellschaft

Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh & Co. Kg

Other

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technology Ag

Infineon Technologies Bipolar Gmbh & Co. Kg

Dr. Ing. H.c. F. Porsche Aktiengesellschaft

Hans-Joachim Schulze

Anton Mauder

Johannes Georg Laven

Franz-Josef Niedernostheide

Franz Hirler

Frank Dieter Pfirsch

Francisco Javier Santos Rodriguez

Werner Schustereder

Roland Rupp

Helmut Strack

Roman Baburske

Peter Irsigler

Moriz Jelinek

Armin Willmeroth

Jens Peter Konrath

Frank Hille

Holger Schulze

Helmut Oefner

Stephan Voss

Johannes Baumgartl

Hans Weber

Matteo Dainese

Thomas Basler

Reiner Barthelmess

Franz Josef Niedernostheide

Ralf Siemieniec

Manfred Pfaffenlehner

Guenther Ruhl

Iris Moder

Hans-Joerg Timme

Elmar Falck

Ingo Muri

Markus Zundel

Wolfgang Lehnert

Alexander Breymesser

Oliver Hellmund

Daniel Schloegl

Christian Jaeger

Rudolf Berger

Erich Griebl

Carsten Schaeffer

Caspar Leendertz

Bernhard Goller

Joachim Mahler

Gerhard Schmidt

Rudolf Elpelt

Sebastian Schmidt

Wolfgang Werner

Uwe Wahl

Wolfgang Bergner

Thomas Aichinger

Antonio Vellei

Andreas Peter Meiser

Carsten Ahrens

Andre Brockmeier

Hermann Gruber

Markus Schmitt

Thoralf Kautzsch

Romain Esteve

Christian Philipp Sandow

Heinz Mitlehner

Ralf Otremba

Edward Fuergut

Dethard Peters

Michael Bernhard Sommer

Manfred Schneegans

Carsten Von Koblinski

Joachim Weyers

Ravi Keshav Joshi

Steffen Bieselt

Alexander Philippou

Roman Knoefler

Marko Swoboda

Daniel Tutuc

Gerald Deboy

Jenoe Tihanyi

Oliver Blank

Manfred Engelhardt

Matthias Stecher

Wolfgang Roesner

Klemens Pruegl

Christian Beyer

Bernhard Weidgans

Stephan Pindl

Juergen Steinbrenner

Friedrich Kroener

Olaf Storbeck

Till Schloesser

Khalil Hosseini

Oliver Haeberlen

Juergen Hoegerl

Ivan Nikitin

Martin Gruber

Irmgard Escher-Poeppel

David Laforet

Herbert Schäfer

Adolf Koller

Michael Rueb

Cedric Ouvrard

Peter Friedrichs

A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. Semiconductor device elements are formed in the semiconductor body by processing the semiconductor body at the first surface. A wiring area is formed over the first surface of the semiconductor body. The semiconductor body is attached to a carrier via the wiring area. Thereafter, ions are implanted through the second surface into the semiconductor body. The ions are ions of a doping element, or ions, which induce doping by complex formation, or ions of a heavy metal. A surface region of the semiconductor body at the second surface is irradiated with a plurality of laser pulses. Thereafter, the carrier is removed from the semiconductor body.

Method of manufacturing a semiconductor device

A semiconductor device includes: a drift region of a first conductivity type arranged between first and second surfaces of a semiconductor body; a first region of the first conductivity type at the second surface; a second region of a second conductivity type adjacent the first region at the second surface; a field stop region of the first conductivity type between the drift region and second surface; and a first electrode on the second surface directly adjacent to the first region in a first part of the second surface and to the second region in a second part of the second surface. The field stop region includes first and second sub-regions. Over a predominant portion of the first part of the second surface, the second sub-region directly adjoins the first region and includes dopants of the second conductivity type that partially compensate dopants of the first conductivity type.

Semiconductor device including a field stop region

A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.

Method of manufacturing a metal silicide layer above a silicon carbide substrate, and semiconductor device comprising a metal silicide layer

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; a trench formed in a first main surface of the semiconductor substrate; a field plate electrode in the trench and reaching a same level as the first main surface of the semiconductor substrate; an insulating material that separates the field plate electrode from the semiconductor substrate; and a material embedded in the field plate electrode. The field plate electrode is made of a different material than the material embedded in the field plate electrode. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. Additional device embodiments and methods of producing the semiconductor device are also described.

Power semiconductor device having an electrode with an embedded material

The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.

Method of manufacturing ohmic contacts on a silicon carbide (SIC) substrate, method of manufacturing a semiconductor device, and semiconductor device

A semiconductor device includes: an n-doped drift region between first and second surfaces of a semiconductor body; a p-doped first region at the second surface; and an n-doped field stop region between the drift and first region. The field stop region includes first and second sub-regions with hydrogen related donors. A p-n junction separates the first region and first sub-region. A concentration of the hydrogen related donors, along a first vertical extent of the first sub-region, steadily increases from the pn-junction to a maximum value, and steadily decreases from the maximum value to a reference value at a first transition between the sub-regions. A second vertical extent of the second sub-region ends at a second transition to the drift region where the concentration of hydrogen related donors equals 10% of the reference value. A maximum concentration value in the second sub-region is at most 20% larger than the reference value.

A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.

Transistor device and method of manufacturing

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

Method for splitting semiconductor wafers

A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

Power semiconductor device and method

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

Methods of forming semiconductor devices in a layer of epitaxial silicon carbide

pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

Manufacturing and reuse of semiconductor substrates

A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 μm; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 μm. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Power semiconductor device

A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

Vertical power semiconductor device and manufacturing method

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Methods for forming a semiconductor device having a second semiconductor layer on a first semiconductor layer

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Taufkirchen, Germany

Hans-Joachim Schulze