Infineon Technologies Ag

Infineon Technologies Austria Ag

Siemens Aktiengesellschaft

Eupec Europaeische Gesellschaft Fuer Leistungshalbleiter Mbh & Co. Kg

Other

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co. Kg

Infineon Technology Ag

Infineon Technologies Bipolar Gmbh & Co. Kg

Hans-Joachim Schulze

Anton Mauder

Johannes Georg Laven

Franz-Josef Niedernostheide

Franz Hirler

Frank Dieter Pfirsch

Francisco Javier Santos Rodriguez

Roland Rupp

Werner Schustereder

Helmut Strack

Roman Baburske

Peter Irsigler

Armin Willmeroth

Jens Peter Konrath

Frank Hille

Helmut Oefner

Holger Schulze

Moriz Jelinek

Stephan Voss

Johannes Baumgartl

Hans Weber

Matteo Dainese

Thomas Basler

Reiner Barthelmess

Franz Josef Niedernostheide

Ralf Siemieniec

Manfred Pfaffenlehner

Guenther Ruhl

Iris Moder

Hans-Joerg Timme

Elmar Falck

Ingo Muri

Markus Zundel

Wolfgang Lehnert

Alexander Breymesser

Oliver Hellmund

Christian Jaeger

Rudolf Berger

Erich Griebl

Carsten Schaeffer

Bernhard Goller

Caspar Leendertz

Joachim Mahler

Gerhard Schmidt

Rudolf Elpelt

Sebastian Schmidt

Winfried Kaindl

Wolfgang Werner

Uwe Wahl

Wolfgang Bergner

Thomas Aichinger

Antonio Vellei

Andreas Peter Meiser

Carsten Ahrens

Andre Brockmeier

Hermann Gruber

Markus Schmitt

Thoralf Kautzsch

Romain Esteve

Christian Philipp Sandow

Heinz Mitlehner

Ralf Otremba

Edward Fuergut

Dethard Peters

Michael Bernhard Sommer

Manfred Schneegans

Carsten Von Koblinski

Joachim Weyers

Steffen Bieselt

Alexander Philippou

Roman Knoefler

Marko Swoboda

Gerald Deboy

Jenoe Tihanyi

Matthias Stecher

Manfred Engelhardt

Wolfgang Roesner

Klemens Pruegl

Ravi Keshav Joshi

Christian Beyer

Bernhard Weidgans

Stephan Pindl

Juergen Steinbrenner

Friedrich Kroener

Olaf Storbeck

Daniel Reznik

Till Schloesser

Oliver Blank

Khalil Hosseini

Oliver Haeberlen

Juergen Hoegerl

Ivan Nikitin

Martin Gruber

Irmgard Escher-Poeppel

David Laforet

Adolf Koller

Michael Rueb

Cedric Ouvrard

Peter Friedrichs

Jörg Dorn

A transistor device is provided. In an example, the transistor device includes a semiconductor body having a first main surface, a second main surface opposite to the first main surface. The transistor device further includes a transistor cell array including a plurality of transistor cells. The transistor cell array includes a first load electrode over the first main surface. The first load electrode is electrically connected to the plurality of transistor cells. The transistor cell array further includes a second load electrode over the second main surface. The second load electrode is electrically connected to the plurality of transistor cells. The plurality of transistor cells includes at least one control electrode including carbon.

Transistor device and method of manufacturing

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device

A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.

Method for splitting semiconductor wafers

A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

Power semiconductor device and method

A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants defining a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.

Methods of forming semiconductor devices in a layer of epitaxial silicon carbide

pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).

Manufacturing and reuse of semiconductor substrates

A power semiconductor device includes, an active area that conducts load current between first and second load terminal structures, a drift region, and a backside region that includes, inside the active area, first and second backside emitter zones one or both of which includes: first sectors having at least one first region of a second conductivity type contacting the second load terminal structure and a smallest lateral extension of at most 50 μm; and/or second sectors having a second region of the second conductivity type contacting the second load terminal structure and a smallest lateral extension of at least 50 μm. The emitter zones differ by at least of: the presence of first and/or second sectors; smallest lateral extension of first and/or second sectors; lateral distance between neighboring first and/or second sectors; smallest lateral extension of the first regions; lateral distance between neighboring first regions within the same first sector.

Power semiconductor device

A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

Vertical power semiconductor device and manufacturing method

A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.

Methods for forming a semiconductor device having a second semiconductor layer on a first semiconductor layer

A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.

Multi-device semiconductor chip with electrical access to devices at either side

A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

Method of producing a semiconductor device having a ferroelectric gate stack

A semiconductor device includes a silicon carbide (SiC) drift zone over a SiC field stop zone and/or a SiC semiconductor substrate. A concentration of Zdefects in the SiC drift zone is at least one order of magnitude smaller than in the SiC field stop zone and/or the SiC semiconductor substrate. Separately or in combination, a concentration of Zdefects in a part of the SiC drift zone is at least one order of magnitude smaller than in another part of the drift zone.

Semiconductor device having a silicon carbide drift zone over a silicon carbide field stop zone

A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.

Semiconductor device having semiconductor device elements in a semiconductor layer

A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a <0001> direction or a <11-23> direction.

Semiconductor device fabricated using channeling implant

A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*10/cm; attaching an acceptor layer at the graphene layer to form a wafer-stack, the acceptor layer comprising silicon carbide having a second defect density higher than the first defect density; forming an epitaxial silicon carbide layer; splitting the wafer-stack along a split plane in the silicon carbide substrate to form a device wafer comprising the graphene layer and a silicon carbide split layer at the graphene layer; and further processing the device wafer at the upper side.

Method for forming a semiconductor device and a semiconductor device

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Taufkirchen, Germany

Hans-Joachim Schulze