Chinese Academy of Sciences

Hangbing Lv

Ming Liu

Qi Liu

Shibing Long

Qing Luo

Xiaoxin Xu

Cheng Lu

Kangwei Zhang

Ling Li

Xumeng Zhang

Writam Banerjee

Wei Wang

Yan Wang

Jie Yu

Bing Chen

Guozhong Xing

Huai Lin

Haitao Sun

Zuheng Wu

Sen Liu

Tiancheng Gong

Danian Dong

Zhaoan Yu

Feng Zhang

Yu Liu

Tuo Shi

Yanhua Wang

Changqing Xie

Keke Zhang

Jianguo Yang

Nianduan Lu

Jiebin Niu

Kaiping Zhang

Xiaolong Zhao

Pengxiao Sun

Haltao Sun

Facai Wu

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

Method of preparing programmable diode, programmable diode and ferroelectric memory

A method for operating a memory cell and a resistive random access memory, and an electronic device are provided. The method for operating a memory cell includes: performing a writing operation and an erasing operation on a resistive device. The writing operation includes: applying a writing voltage on the resistive device; determining whether a resistance value of the resistive device reaches a low resistance state threshold; and applying a constant current to the resistive device in response to the resistance value of the resistive device reaching the low resistance state threshold, wherein a voltage value generated by the constant current on the resistive device is smaller than a voltage value of the writing voltage.

Method for operating memory cell and resistive random access memory, and electronic device

Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer.

Memory cell structure, memory array structure, and voltage biasing method

A self-reference storage structure includes: three transistors, including a first transistor T, a second transistor T, and a third transistor T; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJand a second magnetic tunnel junction MTJ. The first magnetic tunnel junction MTJis connected in series between the first transistor Tand the second transistor T, and the second magnetic tunnel junction MTJis connected in series between the second transistor Tand the third transistor T. When the first transistor T, the second transistor Tand the third transistor Tare turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.

Self-reference storage structure and in-memory computing circuit

A neuron circuit (), including a memristive element (M) used to receive an excitation signal; a trigger element (D) connected to the memristive element (M) and used to receive a clock control signal for the neuron circuit and an output signal of the memristive element (M); a feedback element (T) connected to an output end of the trigger element (D) and an input end of the memristive element (M), and used to control a voltage at the input end of the memristive element (M); and an AND circuit (A) used to perform an AND operation on an output signal of the trigger element (D) and the clock control signal. An output signal of the AND circuit (A) acts as an output signal of the neuron circuit ().

Neuron circuit and neural network circuit

Disclosed is an afferent neuron circuit, which includes: a resistance Rc and a volatile threshold switching device TS, wherein the volatile threshold switching device TS is provided with a parasitic capacitor Cparasitic; a first end of the resistance Rc serves as a signal input terminal, and a second end of the resistance Rc serves as a signal output terminal; and a first end of the volatile threshold switching device TS is connected to the signal output terminal, and a second end of the volatile threshold switching device TS is grounded. The afferent neuron circuit provided in the content of the present disclosure has a simple structure and good scalability and is suitable for large-scale integration.

Afferent neuron circuit and mechanoreceptive system

Disclosed are an artificial sensory nervous circuit and a manufacturing method thereof. The artificial sensory nervous circuit includes a sensor (S), a first memristor (RS), and a neuron circuit, where the first memristor (RS) has a unidirectional resistance characteristic. The sensor (S) is configured to sensing an external signal and generating an excitation signal according to the external signal. The first memristor (RS) is configured to generating a response signal according to the excitation signal. The neuron circuit is configured to perform charging and discharging according to the response signal so as to output a pulse signal. With the artificial sensory nervous circuit and the manufacturing method thereof, sensitivity and habituation characteristics of biological perception are realized by using a simple circuit.

Artificial sensory nervous circuit and manufacturing method thereof

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Complementary storage unit and method of preparing the same, and complementary memory

The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.

Memory circuit structure and method of operating memory circuit structure

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Symmetric memory cell and BNN circuit

Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

Neural network operation device

A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Writing method and erasing method of fusion memory

The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

Spintronic device, SOT-MRAM storage cell, storage array and in-memory computing circuit

The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.

Fusion memory

The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.

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Beijing, China

Hangbing Lv