Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Shanghai Bright Power Semiconductor Co., Ltd.

Powerlite Semiconductor (shanghai) Co., Ltd

Hang Fan

Liang-Yu Su

Ming-Fang Lai

Lei Shi

Feng Han

Hung-Chih Tsai

Shui-Ming Cheng

Shuming Xu

Jian Wu

Luyao Song

A semiconductor structure includes at least a first chip, the first chip comprising a semiconductor substrate and an active layer formed on an upper surface of the substrate, one or more lateral metal-oxide semiconductor devices being formed in the active layer of the first chip. The semiconductor structure further includes at least a first integrated capacitor disposed on a back-side of the semiconductor substrate of the first chip. The first integrated capacitor includes a first conductive layer in electrical connection with the back-side of the substrate, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.

Three-dimensional bipolar-CMOS-DMOS (BCD) structure with integrated back-side capacitor

The present disclosure provides an electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit, a second trigger circuit, a first discharge component and a second discharge component. The first trigger circuit includes a first GaN based transistor, including a first source/drain and a second source/drain coupled to the first reference terminal and a gate coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a terminal coupled to the first reference terminal via the second voltage divider. The first discharge component includes a gate coupled between the first trigger circuit and the first voltage divider. The second discharge component includes a gate coupled between the second trigger circuit and the second voltage divider.

Electrostatic discharge protection circuit and semiconductor circuit

A radio frequency (RF) switch device includes a semiconductor substrate, doped with an impurity of a first conductivity type at a first doping concentration level, and a mesa extending vertically from an upper surface of the substrate and formed contiguous therewith. The mesa includes a drift region doped with the impurity of the first conductivity type at a second doping concentration level, the second doping concentration level being less than the first doping concentration level. The mesa forms a primary current conduction path in the RF switch device. The RF switch device further includes an insulator layer disposed on at least a portion of the upper surface of the substrate and sidewalls of the mesa, and at least one gate disposed on at least a portion of an upper surface of the insulator layer, the gate at least partially surrounding the mesa.

Enhanced radio frequency switch and fabrication methods thereof

A semiconductor device includes a doped region of a first conductivity type in a substrate, a source/drain region of the first conductivity in the doped region, and a gate structure overlapping a portion of the doped region. The semiconductor device further comprises a multi-layer spacer over a first sidewall of the gate structure. The multi-layer spacer comprises a first spacer layer, a second spacer layer over the first spacer layer, and a third spacer layer over the second spacer layer. The first spacer layer and the second spacer layer are in contact with the first sidewall of the gate structure.

Semiconductor device and manufacturing method thereof

The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.

A device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage at a first terminal and receive a second voltage at a second terminal and includes a first trigger circuit and a first resistor. The first trigger circuit includes a first input terminal and a first output terminal. The first input terminal is configured to receive the first voltage. The first resistor is coupled between the first output terminal and the second terminal. When the first voltage received at the first terminal is a first overvoltage and a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch.

Device and method for electrostatic discharge protection

A method includes forming a body region of a first conductivity type and a doped region of a second conductivity type in a semiconductor substrate; forming a gate structure the substrate, and first gate spacers respectively on first and second sides of the gate structure; depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers respectively on the first and second sides of the gate structure; removing a first one of the third gate spacers from the first side of the gate structure, while leaving a second one of the third gate spacers on the second side of the gate structure; and patterning the second spacer layer into a second gate spacer by using the second one of the third gate spacers as an etching mask.

A device is disclosed herein. The device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage and a second voltage. When a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch. When the voltage difference between the first voltage and the second voltage is lower than a second voltage threshold, the ESD driver outputs a second trigger signal to turn on the ESD protection switch.

A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

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Shanghai, China

Hang Fan