Skyworks Solutions, Inc.

Sige Semiconductor, Inc.

Other

Hanching Fuh

Dylan Charles Bartle

Hailing Wang

Paul T DiCarlo

David Scott Whitefield

Jerod F Mason

Guillaume Alexandre Blin

Fikret Altunkilic

Anuj Madan

Yu Zhu

Oleksiy Klimashov

Nuttapong Srirattana

Lui Ray Lam

Steven Christopher Sprinkle

Haki Cebi

Jong-Hoon Lee

Chuming Shih

Lui (Ray) Lam

Mengshu Hsu

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Field-effect transistors with interleaved finger configuration

Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Switch with gate or body connected linearizer

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Main-auxiliary field-effect transistor configurations

A radio frequency (RF) switch arrangement that improves the voltage handling capacity of a stack of switching elements (e.g., field-effect transistors (FETs)). The RF switch arrangement can include a ground plane and a stack arranged in relation to the ground plane, the stack including a plurality of switching elements coupled in series with one another. The RF switch arrangement can also include a plurality of capacitive elements, each of the plurality of capacitive elements providing a capacitive path across respective terminals of a corresponding one of the plurality of switching elements.

Devices and methods related to voltage compensated switch stack

Fabricating field-effect transistors with interleaved source and drain finger configuration

Switches with main-auxiliary field-effect transistor configurations

Voltage compensated switch stack

Main-auxiliary field-effect transistor configurations with an auxiliary stack and interior parallel transistors

Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.

Stacked field-effect transistors having proximity electrodes

The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.

Fabricating field-effect transistors with body contacts between source, gate and drain assemblies

Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Independently controlled main-auxiliary branch configurations for radio frequency applications

Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Non-symmetric body contacts for field-effect transistors

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Allston, MA, United States of America

Hanching Fuh