Samsung Electronics Co., Ltd.

Han Na Jin

Young Gwan Ko

Tae Sung Jeong

Jae Ean Lee

Jung Soo Byun

A semiconductor package includes: a connection structure having first and second surface opposing each other and including a plurality of insulating layers, a plurality of redistribution layers, and a plurality of connection vias; at least one semiconductor chip on the first surface having connection pads electrically connected to the plurality of redistribution layers; an encapsulant on the first surface encapsulating the at least one semiconductor chip; and UBM layers including UBM pads on the second surface and UBM vias connecting a redistribution layer. At least one connection via adjacent to the first surface has a tapered structure narrowed toward the second surface, and the other connection vias and the UBM vias have a tapered structure narrowed toward the first surface.

Method of manufacturing semiconductor package having connection structure with tapering connection via layers

Semiconductor package having a connection structure with tapering connection via layers

A carrier substrate includes a core layer, a first metal layer disposed on the core layer, and a plurality of unit pattern portions disposed on the first metal layer. The plurality of unit pattern portions each have a planar area smaller than a planar area of the first metal layer. The plurality of unit pattern portions each include a second metal layer disposed on the first metal layer, a release layer disposed on the second metal layer, and a third metal layer disposed on the release layer.

Carrier substrate and method of manufacturing semiconductor package using the same

A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.

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Suwon-si, South Korea

Han Na Jin