United Microelectronics Corp.

Han-Min Huang

Chin-Lung Chen

Chun-Yao Lee

Wei-Chun Chang

Hung-Te Lin

Hong-Ze Lin

Wei-Shan Liao

Bo-Jui Huang

Kun-Yi Chou

Ting-Zhou Yan

A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Manufacturing method of anti punch-through leakage current metal-oxide-semiconductor transistor

An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Anti punch-through leakage current metal-oxide-semiconductor transistor and manufacturing method thereof

A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.

Lateral-diffusion metal-oxide-semiconductor device

A method of fabricating a semiconductor device utilizes a substrate including a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. A first well of a first conductivity type is formed. Two separate second wells of a second conductivity type are formed in the first well and two separate isolation structures are formed respectively in the second wells in each of the high voltage circuit area and the medium voltage circuit area. A first gate dielectric layer is formed in the high voltage circuit area. A second gate dielectric layer that is thinner than the first gate dielectric layer is formed in each of the medium voltage circuit area and the low voltage circuit area. A gate is formed. Two source and drain regions of the second conductivity type are respectively formed. The method is simple and low-cost and meets the market requirement.

Method of fabricating semiconductor device

A semiconductor device includes a substrate of a first conductivity type, a first doped region of a second conductivity type, at least one second doped region of the first conductivity type, a third doped region of the second conductivity type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately.

Semiconductor device and method for fabricating the same

A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage device, the medium voltage device and the low voltage device are respectively disposed in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area. The medium voltage device and the high voltage device have the same structure while the medium voltage device and the low voltage device have different structures. Further, the high voltage device, the medium voltage device and the low voltage device respectively include a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.

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Taipei County, Taiwan

Han-Min Huang