Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Hsin Kuo

Fu-Ming Huang

Liang-Guang Chen

Chi-Ming Tsai

Chung-Chi Ko

Neng-Jye Yang

Chin-Hsiang Lin

Chi-Ming Yang

Shwang-Ming Jeng

He Hui Peng

Wen-Chih Chiou

Ching-Hua Hsieh

Hung-Wen Su

Hsien-Ming Lee

Tsu Shih

Shing-Chyang Pan

Ming-Chung Liang

Shich-Chang Suen

Soon-Kang Huang

Huang Soon Kang

He-Hui Peng

Hao-Jen Liao

An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.

Interconnect structure for semiconductor devices

A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SiN) or silicon oxide (SiO), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.

Brush cleaning method

Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.

Mechanisms for removing debris from polishing pad

The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.

Method of fabricating a semiconductor device, and chemical mechanical polish tool

The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Metal conductor chemical mechanical polish

A semiconductor substructure with improved performance and a method of forming the same is described. The method includes providing a semiconductor dielectric layer having a recess formed therein; forming an interconnect structure with a metal liner and a conductive fill within the recess; and applying an electron beam treatment to the substructure.

Interconnects for semiconductor devices

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.

Reduction of OCD measurement noise by way of metal via slots

A brush cleaning system comprising: a plate comprising at least one of silicon nitride (SiN) or silicon oxide (SiO), wherein the plate has a static charge on a surface thereof; and a machine configured to rotate a brush in contact with the static charged surface of the plate.

Brush cleaning system

A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.

Barrier layer for copper interconnect

An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.

Growing community of inventors

Tainan, Taiwan

Han-Hsin Kuo