Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Macroblock, Inc.

Han-Hsiang Huang

Shin-Puu Jeng

Shuo-Mao Chen

Feng-Cheng Hsu

Hsiao-Wen Lee

Hsien-Wen Liu

Chien-Sheng Chen

Yu-Sheng Lin

Yi-Wen Huang

Lon-Kou Chang

Shu-Shen Yeh

Yen-Hao Chen

Chih-Hua Chen

Chen-Cheng Kuo

Kai-Ming Ching

Chih-wei Chang

Ting-Yu Yeh

Chen Chen-Shien

Chun-Hsien Wen

A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.

Power delivery structures and methods of manufacturing thereof

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

Bridging-resistant microbump structures and methods of forming the same

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Multi-chip packages and methods of forming the same

A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.

Basin-shaped underbump plates and methods of forming the same

A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.

Package structure and method of fabricating the same

A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.

Voltage regulator device

Multi-chip packages

A voltage reduction circuit for a bandgap reference voltage circuit is provided, and the voltage reduction circuit includes a first transistor, a current mirror circuit, a voltage dividing circuit, an output resistor, and a fourth transistor. The first transistor receives an initial bandgap reference voltage from the bandgap reference voltage circuit. The voltage dividing circuit has a voltage dividing node for outputting a first dividing voltage. The fourth transistor receives the first divided voltage. The current mirror circuit forms a first current on the voltage dividing circuit through the first transistor, and mirrors the first current to the output resistor to form a second current. The voltage dividing circuit and the output resistor each have a first temperature characteristic, the first transistor and the fourth transistor each have a second temperature characteristic, thereby generating, a reference voltage independent of temperature and lower than the initial bandgap reference voltage.

Voltage reduction circuit for bandgap reference voltage circuit

Multi-chip wafer level packages

A current generation circuit includes a temperature sensing circuit, a resistor element having a resistance, and a current mirror circuit. The temperature sensing circuit is configured to generate a reference voltage having corresponding magnitude according to a temperature of the current generation circuit. The resistor element is coupled with the temperature sensing circuit, and is configured to determine magnitude of a reference current according to the reference voltage and the resistance. The current mirror circuit is coupled with the temperature sensing circuit, and is configured to generate an output current according to the reference current. The temperature sensing circuit and the resistor element both have positive temperature coefficients or negative temperature coefficients.

Current generation circuit

Methods of forming multi-chip wafer level packages

Multi-chip wafer level packages and methods of forming the same

A resonant converter with power factor correction includes a power-obtaining circuit, an energy-storage element and an energy-transferred circuit. The power-obtaining circuit is used for receiving an input line voltage. The energy-storage element is coupled between the power-obtaining circuit and the energy-transferred circuit. The energy-transferred circuit is used for generating an output power. In a first time period, based on a first control signal, the energy-storage element and the power-obtaining circuit operate a soft switching so that the energy-storage element is charged to obtain the input line power and generate an energy-storage voltage. In a second time period, based on a second control signal, the energy-storage element and the energy-transferred circuit operate a soft switching so that the energy-storage element is discharged to make the energy-storage voltage converted into the output power.

Power factor-corrected resonant converter and parallel power factor-corrected resonant converter

A common-core power factor correction resonant converter includes an energy-transforming circuit. The energy-transforming circuit receives an input line voltage and generates an output power. The energy-transforming circuit includes a coupling inductor and a charge-storage capacitor. The coupling inductor and the charge-storage capacitor are charged by the input line voltage in response to a control signal, so as to generate a charge-storage capacitor voltage. When the charge-storage capacitor voltage is charged to a preset voltage level, the coupling inductor and the charge-storage capacitor are discharged according to the control signal. Then, the energy in the coupling inductor and the charge-storage capacitor is transformed to the output load and provide the output voltage or current regulation.

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Hsinchu, Taiwan

Han-Hsiang Huang