Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Chung Chen

Chiarn-Lung Lee

Je Wang

Ji-Chung Huang

Jui-Feng Jao

Hsiang-Lin Lin

Chung-En Hsu

Gary Yang

Chai-Tak Teh

Yuan-Shin Jing

Yuan-Shing Jing

Min-Nin Yu

Jian-Liang Lin

George O Saile

A method of fabricating a stacked dielectric layer for suppressing electrostatic charge buildup. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer by performing a plasma treatment on the dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.

Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup

A method for forming BPSG layers over PECVD silicon oxide layers by atmospheric chemical vapor deposition using ozone and TEOS is described. The method prevents the formation of voids in deep depressions such as are found between metallization lines or closely spaced polysilicon structures in flash memory integrated circuits. The method deposits the BPSG layer at ozone/TEOS flow rate ratio of 12:1 or greater. The voids are caused by excessive shrinkage of the BPSG which produces high stresses in the depressions during planarization reflow causing the BPSG to become detached from the underlying silicon oxide. The voids are measured as line defects in a double polysilicon flash memory circuit. The high ozone/TEOS ratio increases the density of the as-deposited BPSG layer which in turn produces reduced shrinkage of the layer during the subsequent planarization reflow. A correlation is found between BPSG shrinkage and line yield.

Method for preventing delamination of APCVD BPSG films

A method to store wafers, immediately after the deposition of a layer of BPSG, into an environment of dry air or dry N,or dry Ar or a N,O plasma chamber. This storage can occur over a variable period of time and with a variable delay between BPSG deposition and BPSG flow, dependent on which storage environment is applied. The surface of the deposited layer of BPSG is, in doing so, not exposed to H,O and the formation of unstable irregularities on the surface of the deposited BPSG is prevented.

Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition

A method for forming upon a microelectronics layer upon a substrate employed within a microelectronics fabrication a silicon oxide dielectric layer with enhanced density and reduced mobile species, ionic concentration and ionic mobility. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a blanket undoped silicon oxide glass dielectric layer employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) from tetra-ethyl-ortho-silicate (TEOS) vapor, wherein a high flow rate ratio of ozone gas to TEOS vapor affords enhanced density and reduced mobile species, ionic concentration and ionic mobility in the blanket silicon oxide glass dielectric layer. There is then formed a blanket boron-phosphorus doped silicon containing glass dielectric layer over the substrate employing ozone assisted near atmospheric pressure thermal chemical vapor deposition (APCVD) to complete the dielectric layer. The blanket undoped silicon oxide glass dielectric layer serves as a barrier to diffusion of mobile species from the doped silicon containing glass dielectric layer or other dielectric layers to attenuate hot carrier injection effects, which reduces degradation of device reliability.

Formation of dielectric layer employing high

A new method of metal deposition with reduced metal residue after metal etching by cooling the wafer before metal deposition is described. A first patterned conducting layer is provided overlying a dielectric layer on the surface of a semiconductor substrate. The wafer is cooled to a temperature of less than about 20.degree. C. Thereafter, a metal layer is deposited overlying the first patterned conducting layer. The metal layer is etched away where it is not covered by a mask to complete formation of the metal line. Cooling of the wafer before metal deposition decreases the metal residue found after metal etching.

Add one process step to control the SI distribution of Alsicu to

A new method of aluminum plug metallization in the manufacture of an integrated circuit device is described. An insulating layer is provided over the surface of a semiconductor substrate. At least one contact opening is provided through the insulating layer to the semiconductor substrate. A barrier metal layer is deposited over the surface of the insulating layer and within the contact opening. An aluminum layer is sputter deposited over the barrier metal layer and within the contact opening wherein a void is left within the contact opening. The aluminum layer is covered with a dielectric layer wherein the expansion coefficient of the dielectric layer is smaller than the expansion coefficient of the aluminum layer. The aluminum layer is reflowed using rapid thermal annealing wherein the overlying dielectric layer forces the aluminum layer to fill the contact opening completing the metallization in the fabrication of an integrated circuit device.

Aluminum plug process

A method of forming a BPSG dielectric layer on a wafer without delamination in the fabrication of an integrated circuit device wherein a BPSG deposition chamber is used is described. Semiconductor device structures are provided in and on a semiconductor substrate. The BPSG deposition chamber is cleaned according to the following steps. The deposition chamber is cleaned using a fluorine-containing gas. The fluorine-containing gas is pumped out of the deposition chamber wherein residual fluorine-containing gas remains within the deposition chamber. A plasma is flowed into the deposition chamber wherein the plasma consumes all of the residual fluorine-containing gas. The plasma is purged from the deposition chamber to complete the cleaning of the BPSG deposition chamber. Thereafter, a layer of BPSG is deposited over the semiconductor device structures wherein the BPSG layer is deposited while the wafer is within the BPSG deposition chamber. The BPSG layer is flowed wherein no fluorine gas bubble is formed within the BPSG layer to complete the formation of the BPSG dielectric layer on the wafer without delamination in the fabrication of an integrated circuit device.

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Hsin-chu, Taiwan

Han-Chung Chen