Intel Corporation

Hamid Azimi

John Stephen Guzek

Charan K Gurumurthy

Islam A Salama

Ravi Kiran Nalla

Yonggang Li

Javier Soto Gonzalez

Drew W Delaney

Debabrata Gupta

Mirng-Ji Lii

Hwai-Peng Yeoh

Amir Nur Rashid Wagiman

Saliya Witharana

Rahul N Manepalli

Gilroy J Vandentop

Michael Walk

Bob Sankman

Mahadevan Survakumar

Arthur K Lin

Ravi K Nailla

A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method

Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.

Method of forming molded panel embedded die structure

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Forming functionalized carrier structures with coreless packages

A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.

A microelectronic package includes a first substrate () having a first surface area () and a second substrate () having a second surface area (). The first substrate includes a first set of interconnects () having a first pitch () at a first surface () and a second set of interconnects () having a second pitch () at a second surface (). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects () having a third pitch () and internal electrically conductive layers () connected to each other with a microvia (). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Microelectronic package and method of manufacturing same

A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

Method of forming collapse chip connection bumps on a semiconductor substrate

A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.

Method of forming copper layers

A system may include a plurality of pliant conductive elements, a first end of one of the plurality of pliant conductive elements to be electrically coupled to a first electrical contact of an integrated circuit substrate and a second end of the one of the plurality of pliant conductive elements to be electrically coupled to a second electrical contact of an integrated circuit die.

Integrated circuit die/package interconnect

A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.

Integrated circuit package with low modulus layer and capacitor/interposer

Low cost programmable CPU package/substrate

A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.

Method of forming an integrated circuit substrate

An integrated circuit package fabricated by attaching a surface mount pin to a pin pad on a substrate using a Sn&mdash;Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn&mdash;Sb composition has a melting point above the melting point of commonly-used Sn&mdash;Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn&mdash;Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn&mdash;Sb composition, and a flip-chip is attached to the top surface using Sn&mdash;Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn&mdash;Sb solder composition on the bonding surfaces of the pins.

Growing community of inventors

Chandler, AZ, United States of America

Hamid Azimi