Samsung Electronics Co., Ltd.

Hak-Sun Lee

Myeong-Cheol Kim

Kyung-Yub Jeon

Jiwon Kang

Jongmin Baek

Sanghoon Ahn

Wookyung You

Naein Lee

Ji-young Lee

Byunghee Kim

Byung-Kwon Cho

Ki Hyun Park

Vietha Nguyen

YoungWoo Cho

Hoon Seok Seo

Songyi Han

Jiwon Yun

Young-ju Park

Tae Yong Bae

Inoue Naoya

Jongchul Park

Cheol Kyu Kim

Cha-Won Koh

Yong-Joon Choi

Doo-youl Lee

GeumJung Seong

Keunhee Bai

Young-Ju Park

Myeongcheol Kim

Haegeon Jung

Ji-Eun Han

Seungjun Kim

Seungju Park

Je-woo Han

Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.

Integrated circuit devices including enlarged via and fully aligned metal wire and methods of forming the same

A method for forming a fine pattern includes forming line patterns and a connection pattern on a semiconductor substrate, the line patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the connection pattern connecting portions of the line patterns adjacent to each other in the second direction, and performing an ion beam etching process on the connection pattern. The ion beam etching process provides an ion beam in an incident direction parallel to a plane defined by the first direction and a third direction perpendicular to a top surface of the semiconductor substrate, and the incident direction of the ion beam is not perpendicular to the top surface of the semiconductor substrate.

Method for forming a fine pattern

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

Planarized interlayer dielectric with air gap isolation

The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Semiconductor device, electronic device including the same and manufacturing methods thereof

A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about &#xbd; of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.

Method for forming hard mask patterns having a fine pitch and method for forming a semiconductor device using the same

A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

Method of forming fine patterns of semiconductor devices using double patterning

A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.

Method of forming pattern using fine pitch hard mask

A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.

Method for forming fine patterns of a semiconductor device using double patterning

Growing community of inventors

Suwon-si, South Korea

Hak-Sun Lee