Globalfoundries Inc.

Globalfoundries U.S. Inc.

Haiting Wang

Hui Zang

Hong Yu

Scott Beasor

Sipeng Gu

Zhenyu Hu

Jiehui Shu

Ruilong Xie

Guowei Xu

Yanping Shen

Wei Zhao

Judson Robert Holt

Laertis Economikos

Shesh Mani Pandey

Min-Hwa Chi

Jagar Singh

Alexander M Derrickson

Jinping Liu

Ashish Kumar Jha

Yue Zhong

Man Gu

Wei Hua Tong

Yan Ping Shen

Vibhor Jain

Xusheng Kevin Wu

Daniel J Jaeger

Seung Yeon Kim

Tien-Ying Luo

Yiheng Xu

Yong Meng Lee

Hsien-Ching Lo

Wei Hong

Ali Razavieh

Baofu Zhu

Alexander Lee Martin

Chih-Chiang Chang

Hui Zhan

Chung Foong Tan

Chanro Park

Jeffrey Bowman Johnson

Haigou Huang

Yi Qi

Jin Ping Liu

Jerome Ciavatti

David Paul Brunco

Rui Chen

Chun Yu Wong

Tek Po Rinus Lee

Richard Francis Taylor, Iii

Qun Gao

Liu Jiang

Meixiong Zhao

Wang Zheng

Erik Geiss

John H Zhang

Lars W Liebmann

Julien Frougier

Garo Jacques Derderian

Min Gyu Sung

Daniel Chanemougame

Guillaume Bouche

Steven J Bentley

Huang Liu

Shahab Siddiqui

Manfred Eller

Sunil Kumar Singh

Kwan-Yong Lim

Lei Sun

Andreas Knorr

Jianwei Peng

Ravi Prakash Srivastava

Michael Vincent Aquilino

Balaji Kannan

Hongliang Shen

Akshey Sehgal

Xinyuan Dou

Yuping Ren

Arkadiusz Malinowski

Tamilmani Ethirajan

Tao Han

Songkram Srivathanakul

Yongjun Shi

Chang Seo Park

Haifeng Sheng

Jae Gon Lee

Dongyue Yang

Pei Liu

Mankyu Yang

Lixia Lei

Minghao Tang

Chang Ho Maeng

Xing Zhang

Tao Chu

Junsic Hong

Shimpei Yamaguchi

Zhiqing Li

Weihua Tong

Bradley Morgenfeld

Jeffrey Chee

Mitchell Rutkowski

A structure is provided, the structure comprising a substrate and a first silicon germanium fin over the substrate. A first silicon germanium layer may be arranged in the substrate, whereby the first silicon germanium layer may be coupled to the first silicon germanium fin. A second silicon germanium layer may be arranged in the substrate, whereby the second silicon germanium layer may be coupled to the first silicon germanium fin.

Silicon germanium fins and integration methods

Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

Transistors with multiple silicide layers

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate including a trench, and a field-effect transistor including a first and second source/drain regions in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric. The gate and the gate dielectric are disposed laterally between the first and second source/drain regions.

High-voltage semiconductor device structures

An IC structure that includes a trench isolation (TI) in a substrate having three portions of different dielectric materials. The portions may also have different widths. The TI may include a lower portion including a first dielectric material and having a first width, a middle portion including the first dielectric material and an outer second dielectric material, and an upper portion including a third dielectric material and having a second width greater than the first width. The first, second and third dielectric materials are different.

Trench isolation having three portions with different materials, and LDMOS FET including same

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

Bipolar junction transistors with a nanosheet intrinsic base

A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

Fin on silicon-on-insulator

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

The present disclosure relates to semiconductor structures and, more particularly, to a device with a vertical nanowire channel region and methods of manufacture. The structure includes: a bottom source/drain region; a top source/drain region; a gate structure extending between the bottom source/drain region and the top source/drain region; and a vertical nanowire in a channel region of the gate structure.

Field effect transistor with vertical nanowire in channel region and bottom spacer between the vertical nanowire and gate dielectric material

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Lateral bipolar transistor

The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

Single fin structures

Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

Lateral heterojunction bipolar transistor with emitter and/or collector regrown from substrate and method

A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Fin-based lateral bipolar junction transistor with reduced base resistance and method

The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Gate structures

Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

Lateral bipolar transistor structure with base layer of varying horizontal width and methods to form same

Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Semiconductor devices having late-formed isolation structures

Growing community of inventors

Clifton Park, NY, United States of America

Haiting Wang