Semiconductor Manufacturing International (Shanghai) Corporation

Ningbo Semiconductor International Corporation

Semiconductor Manufacturing International Corp.

Haiting Li

Herb He Huang

Clifford Ian Drowley

Jiguang Zhu

Hongtao Ge

Fucheng Chen

Yanghui Xiang

Qiang Zhou

Xinxue Wang

Hongbo Zhao

Xingcheng Jin

Wei Li

Ziru Ren

Yinan Han

Herbhe Huang

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing method are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a piezoelectric film that is located between the first and second cavities and continuously separates these two cavities. The plan views of the first and the second cavities have an overlapped region, which is a polygon that does not have any parallel sides. The piezoelectric film of this inventive concept is a continuous film without any through-hole in it, therefore it can offer improved acoustic resonance performance.

Thin-film bulk acoustic resonator and semiconductor apparatus comprising the same

A semiconductor device includes a first substrate having a first surface and a second surface opposite to the first surface, a shallow trench isolation in the first substrate, the shallow trench isolation having a first depth, the first depth being a distance from a bottom of the shallow trench isolation to the first surface of the first substrate, a transistor on the first surface of the first substrate, a first dielectric cap layer covering the first surface of the first substrate, a first interconnect structure on the first dielectric cap layer, a carrier substrate bonded to the first substrate through the first dielectric cap layer, a second dielectric cap layer on the second surface of the first substrate; and a through silicon via extending through the second dielectric cap layer, the shallow trench isolation, and the first dielectric cap layer, and connected to the first interconnect structure.

Backside processed semiconductor device

A resonator may include a first dielectric member, a second dielectric member, and a composite member. The first dielectric member may have a first cavity. The composite member may include a piezoelectric layer and may overlap at least one of the first dielectric member and the second dielectric member. At least one of the second dielectric member and the composite member may have a second cavity. The piezoelectric layer may be positioned between the first cavity and the second cavity. A projection of the first cavity in a direction perpendicular to a flat side of the first dielectric member and a projection of the second cavity in the direction may intersect each other to form a polygon. No two edges of the polygon may be parallel to each other.

Resonator and related manufacturing method

A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a lower electrode layer and a second dielectric layer; forming a piezoelectric film and an upper electrode layer in an opening in the second dielectric layer; forming a third dielectric layer; forming a first cavity in the third dielectric layer to expose at least part of the upper electrode layer; bonding a first assistant substrate to seal the first cavity; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer on a side of the isolation trench; and etching through the fourth dielectric layer, the isolation trench layer, the first dielectric layer to form a second cavity beneath the lower electrode layer, plan views of the first and second cavities providing an overlapped region having a polygon shape without parallel sides.

Manufacturing of thin-film bulk acoustic resonator and semiconductor apparatus comprising the same

A method for manufacturing a semiconductor apparatus includes: on a base substrate, forming an isolation trench layer, a first dielectric layer, a first metal connecting layer, a piezoelectric film, and an upper electrode layer; forming an acoustic resonance film by patternizing the piezoelectric film, the upper electrode layer, and the first metal connecting layer; above the base substrate, forming a second dielectric layer and a third dielectric layer; forming a first cavity through the third and second dielectric layers, and the protection layer; removing a part of the base substrate to expose the isolation trench layer; forming a fourth dielectric layer under the isolation trench layer; and forming a second cavity through the fourth dielectric layer, the isolation trench layer, and the first dielectric layer, plan views of the first and second cavities forming an overlapped region having a polygon shape without parallel sides.

A resonator may include a first dielectric member, a second dielectric member, a composite member, a first sealer, and a second sealer. The first dielectric member may have a first cavity. The second dielectric member may have a second cavity. The composite member may include a piezoelectric layer and may be positioned between the first cavity and the second cavity. The first sealer may be positioned between two portions of the first dielectric member. The first cavity may be positioned between the first sealer and the composite member. The second sealer may be positioned between two portions of the second dielectric member. The second cavity may be positioned between the second sealer and the composite member.

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The semiconductor device also includes a plurality of transistors on the second semiconductor substrate, a deep trench isolation having a bottom at a surface of the first semiconductor substrate in the second region, the deep trench isolation exposing a sidewall of the second semiconductor substrate and a sidewall of the buried insulating layer, and a dielectric capping layer filling the deep trench isolation and covering the plurality of transistors on the second semiconductor substrate.

Deep trench isolation for RF devices on SOI

A semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.

Inductor device

A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.

A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface. The source and drain terminals are connected to the respective source and drain regions. The transistor device further include a body terminal disposed on the second surface and configured to connect the highest or lowest voltage supply to the semiconductor substrate.

CMOS device with double-sided terminals and method of making the same

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.

Inductor device and fabrication method

A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a front-end device containing a transistor, a radio frequency (RF) device and a first interconnect structure, and a second substrate containing a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate is facing the cavity in the second substrate, and the cavity is over the RF device. Because of the cavity, the distance between the second substrate and the RF device is relatively large so that the second substrate has less impact on the performance of the RF device, thereby improving the performance of the semiconductor device.

Device and method for improving RF performance

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

Method for forming deep trench isolation for RF devices on SOI

In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer.

Growing community of inventors

Shanghai, China

Haiting Li