International Business Machines Corporation

Qualcomm Incorporated

Chartered Semiconductor Manufacturing Ltd (Corporation)

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Globalfoundries Inc.

Other

Kabushiki Kaisha Toshiba

Haining S Yang

Xiangdong Chen

Thomas W Dyer

Chih-Chao Yang

Wai-Kin Li

Keith Kwong Hon Wong

Huilong Zhu

Kangguo Cheng

Junjing Bao

Deok-Kee Kim

Jack Allan Mandelman

Robert C Wong

Xia Li

Dureseti Chidambarrao

Bin Yang

Yanxiang Liu

An L Steegen

Ramachandra Divakaruni

Kern Rim

Zhijiong Luo

Daniel C Edelstein

Oleg Gluschenkov

Ying Di Zhang

Thomas M Shaw

Huajie Chen

Victor Chan

Bruce Bennett Doris

Clement Hsingjen Wann

Louis Lu-Chen Hsu

Brian Joseph Greene

Henry K Utomo

John Jianhong Zhu

Judson Robert Holt

Timothy Joseph Dalton

Matthew Earl Colburn

Ahmet Serkan Ozcan

Periannan Chidambaram

Rajeev Malik

Devendra K Sadana

Anthony K Stamper

Keith E Fogel

Mukta G Farooq

Geng Wang

Joel Pereira De Souza

Shreesh Narasimha

Stanley Seungchul Song

Xiao Hu Liu

Yun-Yu Wang

Zhongze Wang

Charles Thomas Black

Werner A Rausch

Jeffrey Xu

Zhibin Ren

Xinlin Wang

Jun Yuan

Sunfei Fang

Yong Meng Lee

Ying Li

Richard Andre Wachnik

Victor W C Chan

Hung Y Ng

David M Onsongo

Yue Tan

Effendi Leobandung

Ping-Chuan Wang

Soon-Cheon Seo

Michael Patrick Chudzik

Andrew Herbert Simon

Ravikumar Ramachandran

Roger Allen Booth, Jr

Byeong Yeol Kim

Michael P Belyansky

Kaushik Arun Kumar

Changho Jung

Douglas C La Tulipe, Jr

Hongwen Yan

Ye Lu

Xiaojun Yu

Xiaonan Chen

Siddhartha Panda

Anda C Mocuta

Robert J Purtell

Jae-Eun Park

Mark Hoinkis

Kenneth T Settlemyer, Jr

Gaku Sudo

Junedong Lee

Ohsang Kwon

Eng Hua Lim

Noam Jungmann

Hyeokjin Lim

William C Wille

Lixin Ge

Foua Vang

Elazar Kachir

Larry Clevenger

Steffen K Kaldor

Amira Rozenfeld

Douglas La Tulipe

Mukul Gupta

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length; a second gate structure disposed on the substrate and having the first channel length, a first source/drain space between the first gate structure and the second gate structure having a first distance; a third gate structure disposed on the substrate and having a second channel length; and a fourth gate structure disposed on the substrate and having the second channel length, a second source/drain space between the third gate structure and the fourth gate structure having a second distance. In an aspect, the second distance ranges from 0.75 times to 1.25 times the first distance.

Transistors having different channel lengths and comparable source/drain spaces

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate structure disposed on a substrate, a gate spacer adjacent to the gate structure, a source/drain structure adjacent to the gate spacer, a first dielectric layer disposed on the substrate and the source/drain structure, an etch stop spacer over the first dielectric layer and adjacent to the gate spacer, and an etch stop layer over the gate structure, the gate spacer, and the etch stop spacer. The semiconductor structure further includes a source/drain contact extending through the etch stop layer and the first dielectric layer and in contact with the source/drain structure, a sidewall of the source/drain contact adjoining a sidewall of the etch stop layer and a sidewall of the etch stop spacer.

Self-aligned source/drain contact structure and method of manufacturing the same

Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.

Selective contact on source and drain

An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

P-type field effect transistor (PFET) on a silicon germanium (Ge) buffer layer to increase Ge in the PFET source and drain to increase compression of the PFET channel and method of fabrication

A semiconductor device is disclosed that includes a plurality of fins on a substrate. A long channel gate is disposed over a first portion of the plurality of fins. A gate contact is provided having an extended portion that extends into an active area from a gate contact base outside the active area.

FinFET semiconductor device

A metal oxide metal (MOM) capacitor and methods for fabricating the same are disclosed. The MOM capacitor includes a first metal layer having a first plurality of fingers, each of the first plurality of fingers configured to have alternating polarities. A high resistance (Hi-R) conductor layer is disposed adjacent the first metal layer in a plane parallel to the first metal layer.

Back-end-of-line (BEOL) high resistance (Hi-R) conductor layer in a metal oxide metal (MOM) capacitor

Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

Three dimensional (3D) vertical spiral inductor and transformer

In an aspect, a semiconductor device includes a gate. The gate includes a first portion that is located on one end of the gate, a second portion that is located on an opposite end of the gate from the first portion, and a third portion that is located in-between the first portion and the second portion. A first cap located on top of the first portion. A second cap located on top of the second portion. The third portion is capless. A gate contact is located on top of the third portion.

Gate contact isolation in a semiconductor

In some aspects, a semiconductor die includes an insulation layer disposed on a substrate, a gate spacer disposed in the insulation layer, a gate disposed between the gate spacer, a first dielectric gate layer disposed on the gate between the gate spacer, a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer, a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer, and a source/drain contact that has a single inner spacer.

Semiconductor having a source/drain contact with a single inner spacer

Certain aspects are directed to a static random access memory (SRAM) including an SRAM cell with a pass-gate (PG) transistor having increased threshold voltage to improve the read margin of the SRAM cell. The SRAM generally includes a first SRAM cell having a pull-down (PD) transistor and a PG transistor coupled to the PD transistor. In certain aspects, the SRAM includes a second SRAM cell, the second SRAM cell being adjacent to the first SRAM cell and having a PD transistor and a PG transistor coupled to the PD transistor of the second SRAM cell. The SRAM may also include a gate contact region coupled to a gate region of the PG transistor of the first SRAM cell, wherein at least a portion of the gate contact region is offset from a midpoint between the first SRAM cell and the second SRAM cell.

Fin field-effect transistor (FinFET) static random access memory (SRAM) having pass-gate transistors with offset gate contact regions

Methods, systems, and devices for an artificial neural network are described. In one example, an artificial neuron in an artificial neural network may include a resistor coupled with an input line and configured to indicate a synaptic weight and a fuse coupled with the resistor. The artificial neuron may also include a selection component coupled with the fuse and configured to activate the fuse for programming the resistor, and a second selection component coupled with the resistor and an output line, the second selection component configured to select the resistor for a read operation.

Artificial neural networks with precision weight for artificial intelligence

Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate.

Nanosheet (NS) and fin field-effect transistor (FinFET) hybrid integration

An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

Integrated device comprising transistor coupled to a dummy gate contact

Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

Semiconductor device implemented with buried rails

A transistor channel profile structure may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include different fin profiles for the NMOS transistors and the PMOS transistors, such as the NMOS fins are thicker than the PMOS fins or the NMOS fin has a straight vertical surface and the PMOS fin has a notch at a fin bottom region. In still another example, a transistor circuit may include different nano-sheet profiles for a NMOS GAA device and a PMOS GAA device where the NMOS nano-sheet is thicker than the PMOS nano-sheet. Such configurations optimize the NMOS and the PMOS transistors with the NMOS having a low channel resistance while the PMOS has a lower short channel effect.

Device channel profile structure

Growing community of inventors

Wappingers Falls, NY, United States of America

Haining S Yang