United Microelectronics Corp.

United Integrated Circuits Corp.

H J Wu

Gary Y Hong

Chen-Chiu Hsue

Tri-Rung Yew

Shih-Wei Sun

Jacob Chen

Liang-Choo Hsia

Shyi-Long Shy

Lawrence Y Lin

A proximity effect correction method for mask production by integrating the electron beam proximity effect correction method and the optical proximity effect correction method such that the problems of having too large a computer-aided design pattern data file during mask production and using the mask to transfer the image to the wafer by a stepper is solved. The correction method of this invention comprises the steps of providing a pattern for forming on a mask, and then dividing the mask area into a plurality of first area patches and a plurality of second area patches, wherein each first area patch contains part of the whole pattern while each second area patch does not contain any pattern. Next, according to pattern density and light contrast, the amount of exposure by electron beam is adjusted such that electron beam proximity effect and optical proximity effect are corrected forming a corrected pattern. Finally, using the corrected pattern, an electron beam exposure operation is carried out to form the mask.

Proximity effect correction method for mask production

A method of fabricating an embedded dynamic random access memory. Using the method of dual damascence, by forming patterning only one dielectric layer, the contact windows with different depth are formed. In addition, the metal layer formed within the metal connecting regions are used as interconnects without further process.

Method of fabricating embedded dynamic random access memory

An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits. A titanium nitride layer is deposited over the device and within the various contact vias through the planarized oxide layer. A capacitor dielectric layer is provided over the device and then the capacitor dielectric layer is selectively removed from at least the contact vias that become bit line contacts and logic interconnects. A layer of tungsten is deposited and patterned to provide upper capacitor electrodes and to complete the bit line contacts and logic interconnects. This first level tungsten layer also can provide bit line wiring. The 1/2 V.sub.cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring also used by the logic circuits.

Process and structure for embedded DRAM

A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.

Process on thickness control for silicon-on-insulator technology

A manufacturing system and method for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation on a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched tunnel joined and communicating with the controlled environment. A means is provided for maintaining a clean environment in the tunnel. Within the tunnel there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system.

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Hsinchu, Taiwan

H J Wu